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| M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER with ON-SCREEN DISPLAY CONTROLLER REJ03B0134-0100Z Rev.1.00 Oct 01, 2002 1. DESCRIPTION The M37221M4H/M6H/M8H/MAH-XXXSP/FP are single-chip microcomputers designed with CMOS silicon gate technology. They have a OSD, I2C-BUS interface, and PWM, making them perfect for TV channel selection system. The M37221EASP/FP have a built-in PROM that can be written electrically. OSD function Display characters .................................... 24 characters 5 2 lines (3 lines or more can be displayed by software) Kinds of characters ........................................................ 256 kinds Character display area .............................................. 12 16 dots Kinds of character sizes ..................................................... 3 kinds Kinds of character colors .................................. 8 colors (R, G, B) Coloring unit ................... character, character background, raster Display position ............................................................................. Horizontal: 64 levels Vertical: 128 levels Attribute .............................................................................. border 2. FEATURES of basic instructions ..................................................... 71 size ROM ............. 16K bytes (M37221M4H-XXXSP/FP) 24K bytes (M37221M6H-XXXSP/FP) 32K bytes (M37221M8H-XXXSP/FP) 40K bytes (M37221MAH-XXXSP/FP, M37221EASP/FP) RAM ............. 384 bytes (M37221M4H-XXXSP/FP) 448 bytes (M37221M6H-XXXSP/FP) 576 bytes (M37221M8H-XXXSP/FP) 704 bytes (M37221MAH-XXXSP/FP, M37221EASP/FP) (ROM correction memory included) The minimum instruction execution time ......................................... 0.5 s (at 8 MHz oscillation frequency) Power source voltage .................................................. 5 V 10 % Subroutine nesting maximum 96 levels (M37221M4H/M6H-XXXSP/FP) maximum 128 levels (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP) Interrupts ........................................................ 14 types, 14 vectors 8-bit timers ................................................................................... 4 Programmable I/O ports (Ports P0, P1, P2, P30-P32 ) ..................................................... 27 Input ports (Ports P33, P34) ......................................................... 2 Output ports (Ports P52-P55) ...................................................... 4 LED drive ports ............................................................................ 4 Serial I/O ............................................................. 8-bit 1 channel Multi-master I2C-BUS interface ............................... 1 (2 systems) A-D comparator (6-bit resolution) ................................. 6 channels D-A converter (6-bit resolution) .................................................... 2 Note: Only M37221EASP/FP has D-A converter. Number Memory 3. APPLICATION TV output circuit .......................................... 14-bit 1, 8-bit 6 dissipation .............................. High-speed mode : 165 mW (at VCC=5.5V, 8 MHz oscillation frequency, and OSD on) ROM correction function ................................................. 2 vectors PWM Power Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 1 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP TABLE OF CONTENTS 1. DESCRIPTION ............................................................... 1 2. FEATURES .................................................................... 1 3. APPLICATION ................................................................ 1 4. PIN CONFIGURATION .................................................. 3 5. FUNCTIONAL BLOCK DIAGRAM ................................. 5 6. PERFORMANCE OVERVIEW ....................................... 6 7. PIN DESCRIPTION ........................................................ 8 8. FUNCTIONAL DESCRIPTION ..................................... 12 8.1 CENTRAL PROCESSING UNIT (CPU) ......... 12 8.2 MEMORY ....................................................... 13 8.3 INTERRUPTS ................................................ 19 8.4 TIMERS .......................................................... 24 8.5 SERIAL I/O ..................................................... 27 8.6 MULTI-MASTER I2C-BUS INTERFACE ........ 31 8.7 PWM OUTPUT FUNCTION ........................... 44 8.8 A-D COMPARATOR ....................................... 49 8.9 D-A CONVERTER .......................................... 51 8.10 ROM CORRECTION FUNCTION ................ 53 8.11 OSD FUNCTIONS ........................................ 54 8.11.1 Display Position .............................. 58 8.11.2 Character Size ................................ 62 8.11.3 Clock for OSD ................................. 64 8.11.4 Memory for OSD ............................. 65 8.11.5 Color Register ................................. 68 8.11.6 Border ............................................. 70 8.11.7 Multiline Display .............................. 71 8.11.8 OSD Output Pin Control ................. 72 8.11.9 Raster Coloring Function ................ 73 8.12 SOFTWARE RUNAWAY DETECT FUNCTION ... 74 8.13 RESET CIRCUIT .......................................... 75 8.14 CLOCK GENERATING CIRCUIT ................. 76 8.15 DISPLAY OSCILLATION CIRCUIT .............. 77 8.16 AUTO-CLEAR CIRCUIT ............................... 77 8.17 ADDRESSING MODE .................................. 77 8.18 MACHINE INSTRUCTIONS ......................... 77 9. PROGRAMMING NOTES ............................................ 77 10. ABSOLUTE MAXIMUM RATINGS ............................. 78 11. RECOMMENDED OPERATING CONDITIONS ......... 78 12. ELECTRIC CHARACTERISTICS .............................. 79 13. A-D COMPARISON CHARACTERISTICS ................. 81 14. D-A CONVERSION CHARACTERISTICS ................. 81 15. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS .... 81 16. PROM PROGRAMMING METHOD ........................... 82 17. DATA REQUIRED FOR MASK ORDERS .................. 83 18. ONE TIME PROM VERSION M37221EASP/FP MARKING ..... 84 19. APPENDIX ................................................................. 85 20. PACKAGE OUTLINE ................................................ 110 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 2 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 4. PIN CONFIGURATION HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC Outline 42P4B Fig. 4.1 Pin Configuration (1) (Top View) M37221M4H/M6H/M8H/MAH-XXXSP P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 1 2 3 4 42 41 40 39 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 M37221M4H/M6H/M8H/MAH-XXXFP 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC 23 22 Outline 42P2R-A/E Fig. 4.2 Pin Configuration (2) (Top View) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 3 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34 VCC M37221EASP 9 10 11 12 13 14 15 16 17 18 19 20 21 34 33 32 31 30 29 28 27 26 25 24 23 22 Outline 42P4B Fig. 4.3 Pin Configuration (3) (Top View) P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 M37221EAFP 9 10 11 12 13 14 15 16 17 18 19 20 21 34 33 32 31 30 29 28 27 26 25 24 23 22 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34 VCC Outline 42P2R-A/E Fig. 4.4 Pin Configuration (4) (Top View) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 4 of 110 Clock input Clock output XIN XOUT ( ) Timing output VCC VSS CNVSS 18 24 23 21 22 25 Reset input RESET Input ports P33, P34 Clock input for display Clock output for display OSC1 OSC2 SIN SCLK SOUT PWM5 PWM4 PWM3 PWM2 PWM1 PWM0 P0 (8) INT3 P1 (8) P3 (3) P2 (8) INT2 INT1 OUT2 OUT1 B G R 10 9 8 7 6 5 4 3 16 17 26 27 28 29 30 31 32 33 34 35 15 14 13 12 11 36 37 38 39 40 41 42 I/O port P0 I/O port P1 I/O port P2 D-A I/O ports P30-P32 Output ports P52-P55 Notes Only M37221EASP/FP has D-A converter. VSYNC HSYNC Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z TIM2 TIM3 19 20 Clock generating circuit Timer count source selection circuit Fig. 5.1 Functional Block Diagram of M37221 Program counter 5. FUNCTIONAL BLOCK DIAGRAM M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP page 5 of 110 ROM Timer 1 T1 (8) Timer 2 T2 (8) Timer 3 T3 (8) Control signal Instruction decoder Instruction register (8) OSD circuit Timer 4 T4 (8) PCL (8) Index register X (8) Index register Y (8) Stack pointer S (8) 14-bit PWM circuit Data bus RAM Program counter PCH (8) Address bus 8-bit arithmetic and logical unit Accumulator A (8) Processor status register PS (8) A-D comparator Multi-master I 2C-BUS interface D-A converter (See note) SI/O(8) 8-bit PWM circuit ROM correction function P5 (4) 21 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 6. PERFORMANCE OVERVIEW Table 6.1 Performance Overview Parameter Number of basic instructions Number of basic instructions Instruction execution time Memory size ROM M37221M4H-XXXSP/FP M37221M6H-XXXSP/FP M37221M8H-XXXSP/FP M37221MAH-XXXSP/FP, M37221EASP/FP RAM M37221M4H-XXXSP/FP M37221M6H-XXXSP/FP M37221M8H-XXXSP/FP M37221MAH-XXXSP/FP, M37221EASP/FP OSD ROM OSD RAM tInput/Output ports P0 P10, P15-P17 P11-P14 P20, P21 P22-P27 P30, P31 P32 P33, P34 P52-P55 Serial I/O Multi-master I2C-BUS interface A-D comparator D-A converter PWM output circuit Timers ROM correction function Subroutine nesting M37221M4H/M6H-XXXSP/FP M37221M8H/MAH-XXXSP/FP, M37221EASP/FP Interrupt I/O I/O I/O I/O I/O I/O I/O Input Output 71 0.5 s (the minimum instruction execution time, at 8 MHz oscillation fre quency) 8 MHz (maximum) 16K bytes 24K bytes 32K bytes 40K bytes 384 bytes (ROM correction memory included) 448 bytes (ROM correction memory included) 576 bytes (ROM correction memory included) 704 bytes (ROM correction memory included) 8 K bytes 96 bytes 8-bit 5 1 (N-channel open-drain output structure, can be used as PWM output pins, INT input pins, A-D input pin) 4-bit 1 (CMOS input/output structure, can be used as OSD output pin, A-D input pins, INT input pin) 4-bit 1 (CMOS input/output structure, can be used as multi-master I2CBUS interface) 2-bit 1 (CMOS input/output or N-channel open-drain output structure, can be used as serial I/O pins) 6-bit 1 (CMOS input/output structure, can be used as serial input pin, timer external clock input pins) 2-bit 1 (CMOS input/output or N-channel open-drain output structure, can be used as A-D input pins, D-A conversion output pins Clock generating circuit Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 6 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Table 6.2 Performance Overview (continued) Parameter OSD display function Number of display characters Dot structure Kinds of characters Kinds of character sizes Character font coloring Display position Power source voltage Power dissipation OSD ON OSD OFF In stop mode Operating temperature range Device structure Package M37221M4H/M6H/M8H/MAH-XXXSP, M37221EASP M37221M4H/M6H/M8H/MAH-XXXFP, M37221EAFP 24 characters 2 lines 12 16 dots 256 kinds 3 kinds 1 screen: 8 kinds (per character unit) Horizontal: 64 levels, Vertical: 128 levels 5 V 10 % 165 mW typ. (at oscillation frequency f(XIN) = 8 MHz, fOSC = 8 MHz) 110 mW typ. (at oscillation frequency f(XIN) = 8 MHz) 1.65 mW (maximum) -10 C to 70 C CMOS silicon gate process 42-pin plastic molded SDIP 42-pin plastic molded SSOP Functions Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 7 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 7. PIN DESCRIPTION Table 7.1 Pin Description Pin VCC, VSS. CNVSS RESET Name Power source Input/ Output Name Apply voltage of 5 V 10 % (typical) to VCC, and 0 V to VSS. CNVSS Reset input Input This is connected to VSS. To enter the reset state, the reset input pin must be kept at a "L" for 2 s or more (under normal VCC conditions). If more time is needed for the quartz-crystal oscillator to stabilize, this "L" condition should be maintained for the required time. This is the input pin for the main clock generating circuit. To control generating frequency, an external ceramic resonator or a quartz-crystal oscillator is connected between pins XIN and XOUT. If an external clock is used, the clock source should be connected to the XIN pin and the XOUT pin should be left open. Port P0 is an 8-bit I/O port with a direction register allowing each I/O bit to be individually programmed as input or output. At reset, this port is set to input mode. The output structure is N-channel open-drain output (See note 1.) Output Pins P00 to P05 are also used as PWM output pins PWM0 to PWM4, respectively. The output structure is N-channel open-drain output. Pins P06, P07 are also used as external interrupt input pins INT2 and INT1 respectively. P06 pin is also used as analog input pin A-D4. I/O Port P1 is a 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output (See note 1.) Pins P10 is also used as OSD output pin OUT2. The output structure is CMOS output. Pins P11-P14 are used as SCL1, SCL2, SDA1 and SDA2 respectively, when multi-master I2C-BUS interface is used. The output structure is N-channel open-drain output. Pins P15-P17 are also used as analog input pins A-D1 to A-D3 respectively. P15 pin is also used as external interrupt input pin INT3. Port P2 is an 8-bit I/O port and has basically the same functions as port P0. The output structure is CMOS output. The output structure is CMOS output (See note 1.) Pins P23, P24 are also used as timer external clock input pins TIM3, TIM2 respectively. P20 pin is also used as serial I/O synchronizing clock input/output pin SCLK. The output structure is N-channel open-drain output. Pins P21, P22 are also used as serial I/O data input/output pins SOUT, SIN respectively. The output structure is N-channel open-drain output. Ports P30-P32 are a 3-bit I/O port and has basically the same functions as port P0. Either CMOS output or N-channel open-drain output structure can be selected as the port P30 and P31. The output structure of port P32 is N-channel open-drain output. (See notes 1, 2) Pins P30, P31 are also used as analog input pins A-D5, A-D6 respectively. Pins P30, P31 are also used as D-A conversion output pins DA1, DA2 respectively. (See note 3) Ports P33, P34 are a 2-bit input port. P33 pin is also used as OSD clock input pin OSC1. P34 pin is also used as OSD clock output pin OSC2. The output structure is CMOS output. XIN XOUT Clock input Clock output Input Output I/O P00/PWM0- I/O port P0 P05/PWM5, P06/INT2/ A-D4, PWM output P07/INT1 External interrupt input Analog input P10/OUT2, P11/SCL1, P12/SCL2, P13/SDA1, P14/SDA2, P15/A-D1/ INT3, P16/A-D2, P17/A-D3 P20/SCLK, P21/SOUT, P22/SIN, P23/TIM3, P24/TIM2, P25-P27 I/O port P1 OSD output Multi-master I2C-BUS interface Analog input External interrupt input I/O port P2 Timer external clock input Serial I/O synchronizing clock input/ output Serial I/O data input/output P30/A-D5/ DA1, P31/A-D6/ DA2, P32 I/O port P3 Output Input Input I/O Output I/O Input Input I/O Input I/O I/O I/O Analog input D-A conversion output Input Output Input Input Output P33/OSC1, Input port P3 P34/OSC2 Clock input for OSD Clock output for OSD Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 8 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Table 7.2 Pin Description (continued) P52/R, P53/G, P54/B, P55/OUT1 HSYNC VSYNC D-A Output port P5 OSD output HSYNC input VSYNC input DA output Output Output Input Input Output Ports P52-P55 are a 4-bit output port. The output structure is CMOS output. Pins P52-P55 are also used as OSD output pins R, G, B, OUT1 respectively. The output structure is CMOS output. This is a horizontal synchronizing signal input for OSD. This is a vertical synchronizing signal input for OSD. This is a 14-bit PWM output pin. Note 1 : Port Pi (i = 0 to 3) has a port Pi direction register that can be used to program each bit for input ("0") or an output ("1"). The pins programmed as "1" in the direction register are output pins. When pins are programmed as "0," they are input pins. When pins are programmed as output pins, the output data is written into the port latch and then output. When data is read from the output pins, the data of the port latch, not the output pin level, is read. This allows a previously output value to be read correctly even if the output LOW voltage has risen due to, for example, a directly-driven light emitting diode. The input pins are in the floating state, so the values of the pins can be read. When data is written to the input pin, it is written only into the port latch, while the pin remains in the floating state. 2 : To swich output structures, set by the following bits. P30 : bit 0 of port P3 output mode control register P31 : bit 1 of port P3 output mode control register When "0," CMOS output; when "1," N-channel open-drain output. 3: Only M37221EASP/FP have a built-in D-A converter. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 9 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Ports P00-P05, P32 N-channel open drain output Direction register Ports P00-P05, P32 Data bus Port latch Note: Each port is also used as follows: P00-P05 : PWM0-PWM5 Ports P1, P2, P30, P31 Direction register CMOS output Ports P1, P2, P30, P31 Data bus Port latch Notes 1: Each port is also used as follows: P10 : OUT2 P11 : SCL1 P12 : SCL2 P13 : SDA1 P14 : SDA2 P15 : A-D1/INT3 P16 : A-D2 P17 : A-D3 2: The output structure of ports P11-P14 is N-channel open-drain output when using as multi-master I2C-BUS inter face (it is the same with ports P06 and P07 ) 3: The output structure of ports P30 and P31 can be selected either CMOS output or N-channel open-drain output (it is the same with ports P06 and P07 ) P20 : SCLK P21 : SOUT P22 : SIN P23 : TIM3 P24 : TIM2 P30 : A-D5/DA1 P31 : A-D6/DA2 Ports P06, P07 N-channel open-drain output Direction register Ports P06, P07 Data bus Port latch Note: Each port is also used as follow: P06 : INT2/A-D4 P07 : INT1 Fig. 7.1 I/O pin block diagram (1) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 10 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP HSYNC, VSYNC D-A, R, G, B, OUT1, OUT2 Schmidt input Internal circuit HSYNC, VSYNC Internal circuit CMOS output D-A, R, G, B, OUT1, OUT2 Note: Each pin is also used as below: R : P52 G : P53 B : P54 OUT1 : P55 OUT2 : P10 Fig. 7.2 I/O pin block diagram (2) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 11 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8. FUNCTION BLOCK DESCRIPTION 8.1 CENTRAL PROCESSING UNIT (CPU) This microcomputer uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the SERIES 740 8.1.1 CPU Mode Register The CPU mode register includes a stack page selection bit and internal system clock selection bit. The CPU mode register is allocated to address 00FB16. CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 11111 00 CPU mode register (CM) [Address 00FB16] B Name Functions After reset R W Indeterminate 0, 1 Fix these bits to "0." 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page RW RW RW 1 Indeterminate 3 to 7 Fix these bits to "1." Note: This bit is set to "1" after the reset release. Fig. 8.1.1 CPU Mode Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 12 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.2 MEMORY 8.2.1 Special Function Register (SFR) Area The special function register (SFR) area in the zero page includes control registers such as I/O ports and timers. 8.2.6 Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. 8.2.7 Zero Page The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area is possible with only 2 bytes in the zero page addressing mode. 8.2.2 RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. 8.2.3 ROM ROM is used for storing user programs as well as the interrupt vector area. 8.2.8 Special Page The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area is possible with only 2 bytes in the special page addressing mode. 8.2.4 OSD RAM RAM used for specifying the character codes and colors for display. 8.2.5 OSD ROM ROM used for storing character data for display. 8.2.9 ROM Correction Memory (RAM) This is used as the program area for ROM correction. M37221M4 H/M6H -XXXSP/FP 000016 Zero page M37221M6HXXXSP/FP RAM (448 bytes) M37221M4HXXXSP/FP RAM (384 bytes) 00C016 SFR area 00FF16 017F16 01BF16 02C016 02E016 02FF16 OSD RAM (96 bytes) (See note) 060016 06B716 Not used M37221M6HXXXSP/FP ROM (24K bytes) A00016 C00016 OSD ROM (8K bytes) 1000016 11FFF16 Not used ROM correction function Vector 1: address 02C016 Vector 2: address 02E016 Not used Not used M37221M4HXXXSP/FP ROM (16K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.4 OSD RAM. Fig. 8.2.1 Memory Map (M37221M4H/M6H-XXXSP/FP) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 13 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP M37221M8H/MAH-XXXSP/FP, M37221EASP/FP 000016 Zero page 00C016 SFR area 00FF16 M37221MAHXXXSP/FP, M37221EASP/FP RAM (704 bytes) M37221M8HXXXSP/FP RAM (576 bytes) 01FF16 021716 021B16 02C016 02E016 02FF16 030016 033F16 03BF16 Not used OSD RAM (96 bytes) (See note) M37221MAHXXXSP/FP, M37221EASP/FP RAM (40K bytes) M37221M8HXXXSP/FP RAM (32K bytes) 060016 06B716 Not used 600016 800016 Not used 2 page register Not used ROM correction function Vector 1: address 02C016 Vector 2: address 02E016 1000016 OSD ROM (8K bytes) 11FFF16 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.4 OSD RAM. Fig. 8.2.2 Memory Map (M37221M8H/MAH-XXXSP/FP, M37221EASP/FP) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 14 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP SFR area (addresses C016 to DF16) Name State immediately after reset> 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register Bit allocation b7 State immediately after reset b0 b7 b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) 0 0 0 Port P5 (P5) Port P5 direction register (D5) Port P3 output mode control register (P3S) (Note 1) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2 C data shift register (S0) I2 C address register (S0D) I2 C status register (S1) I2 C control register (S1D) I2 C clock control register (S2) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) (Note 2) DA2 conversion register (DA2) (Note 2) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 PN4 PN3 PN2 DA2S DA1S P31S P30S 0 0 ? 0 0 ? SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB BSEL1 BSEL0 10BIT SAD PIN AL AAS AD0 LRB ALS ES0 BC2 BC1 BC0 0 0 0 ACK ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 BIT MODE SM6 SM5 0 SM3 SM2 SM1 SM0 0 0 DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20 0 0 0 0 ? ? ? 0016 ? 0016 ? 0016 ?? 0016 ? ? ?? 0016 ? 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ?? ?? ? ? ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? Note 1: As for M37221M4H/M6H/M8H/MAH-XXXSP/FP, fix bits 2 and 3 to "0." 2: M37221M4H/M6H/M8H/MAH-XXXSP/FP do not have this register. Fix this register to "0016." Fig. 8.2.3 Memory Map of Special Function Register (SFR) (1) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 15 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP SFR area (addresses E016 to FF16) Name Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation b0 b7 HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20 State immediately after reset b0 Horizontal register (HR) Vertical register 1 (CV1) Vertical register 2 (CV2) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) OSD control register (CC) OSD port control register (CRTP) OSD clock selection register (CK) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) 0 0 0 0 ? ? 0 0 ? ? 0 0 CS21 CS20 CS11 CS10 MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10 CC7 CC2 CC1 CC0 OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC 0 0 0 0 ADM4 0 0 CK1 CK0 ADM2 ADM1 ADM0 0 0 0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 0 T12M4 T12M3 T12M2 T12M1 T12M0 T34M5 T34M4 T34M3 T34M2 T34M1 T34M0 Interrupt input polarity register (RE) Test register (TEST) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0 1 IT3R RE5 RE4 RE3 CK0 0 CM2 0 0 0 0 1 0 1 0 1 1 1 0016 11 MSR CK 0 IICR VSCR CRTR TM4R TM3R TM2R TM1R 0 0 0 0 S1R 1T2R 1T1R IT3E IICE VSCE CRTE TM4E TM3E TM2E TM1E MSE 0 S1E 1T2E 1T1E 0016 ?? ?? ? 0? 00 0016 0016 0016 0016 0016 ? 0016 0016 ?0 0016 FF16 0716 FF16 0716 0016 0016 ? ? ? CK0 0 0 0016 11 0016 0016 0016 0016 ? ? ? ? ? ? ? 0 ? ? ? ? 0 0 0 0 1 0 0 ? 0 Fig. 8.2.4 Memory Map of Special Function Register (SFR) (2) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 16 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 2 page register area (addresses 21716 to 21B16) Name State immediately after reset> 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 21716 21816 21916 21A16 21B16 Register ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) Bit allocation b7 State immediately after reset b 0 b7 b0 0 0 RCR1 RCR0 0016 0016 0016 0016 0016 Note: Only M37221M4H/M6H/ M8H /MAH-XXXSP/FP and M37221EASP/FP have 2 pag.e register. Fig. 8.2.5 Memory Map of 2 Page Register Area Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 17 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Name Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Fig. 8.2.6 Internal State of Processor Status Register and Program Counter at Reset Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 18 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.3 INTERRUPTS Interrupts can be caused by 14 different sources comprising 4 external, 8 internal, 1 software, and 1 reset interrupts. Interrupts are vectored interrupts with priorities as shown in Table 8.3.1. Reset is also included in the table as its operation is similar to an interrupt. When an interrupt is accepted, The contents of the program counter and processor status register are automatically stored into the stack. The interrupt disable flag I is set to "1" and the corresponding interrupt request bit is set to "0." The jump destination address stored in the vector address enters the program counter. Other interrupts are disabled when the interrupt disable flag is set to "1." All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit. The interrupt request bits are in Interrupt Request Registers 1 and 2 and the interrupt enable bits are in Interrupt Control Registers 1 and 2. Figures 8.3.2 to 8.3.6 show the interrupt-related registers. Interrupts other than the BRK instruction interrupt and reset are accepted when the interrupt enable bit is "1," interrupt request bit is "1," and the interrupt disable flag is "0." The interrupt request bit can be set to "0" by a program, but not set to "1." The interrupt enable bit can be set to "0" and "1" by a program. Reset is treated as a non-maskable interrupt with the highest priority. Figure 8.3.1 shows interrupt controls. 8.3.1 Interrupt Causes (1) VSYNC, OSD interrupts The VSYNC interrupt is an interrupt request synchronized with the vertical sync signal. The OSD interrupt occurs after character block display to the CRT is completed. (2) INT1 to INT3 external interrupts The INT1 to INT3 interrupts are external interrupt inputs, the system detects that the level of a pin changes from LOW to HIGH or from HIGH to LOW, and generates an interrupt request. The input active edge can be selected by bits 3 to 5 of the interrupt input polarity register (address 00F916) : when this bit is "0," a change from LOW to HIGH is detected; when it is "1," a change from HIGH to LOW is detected. Note that both bits are cleared to "0" at reset. (3) Timers 1 to 4 interrupts An interrupt is generated by an overflow of timers 1 to 4. Table 8.3.1 Interrupt Vector Addresses and Priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Interrupt Source Reset OSD interrupt INT2 external interrupt INT1 external interrupt Timer 4 interrupt f(XIN)/4096 interrupt VSYNC interrupt Timer 3 interrupt Timer 2 interrupt Timer 1 interrupt Serial I/O interrupt Multi-master I2C-BUS interface interrupt INT3 external interrupt BRK instruction interrupt Vector Addresses FFFF16, FFFE16 FFFD16, FFFC16 FFFB16, FFFA16 FFF916, FFF816 FFF516, FFF416 FFF316, FFF216 FFF116, FFF016 FFEF16, FFEE16 FFED16, FFEC16 FFEB16, FFEA16 FFE916, FFE816 FFE716, FFE616 FFE516, FFE416 FFDF16, FFDE16 Remarks Non-maskable Active edge selectable Active edge selectable Active edge selectable Non-maskable Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 19 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP (4) Serial I/O interrupt This is an interrupt request from the clock synchronous serial I/O function. (5) f(XIN)/4096 interrupt The f (XIN)/4096 interrupt occurs regularly with a f(XIN)/4096 period. Set bit 0 of PWM output control register 1 to "0." Interrupt request bit Interrupt enable bit (6) Multi-master I2C-BUS interface interrupt This is an interrupt request related to the multi-master I2C-BUS interface. Interrupt disable flag I BRK instruction Reset Interrupt request (7) BRK instruction interrupt This software interrupt has the least significant priority. It does not have a corresponding interrupt enable bit, and it is not affected by the interrupt disable flag I (non-maskable). Fig. 8.3.1 Interrupt Control Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 20 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued Timer 2 interrupt 0 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (CRTR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued 0 0 : No interrupt request issued INT3 external interrupt request bit (IT3R) 1 : Interrupt request issued RW R R R R R R R R : "0" can be set by software, but "1" cannot be set. Fig. 8.3.2 Interrupt Request Register 1 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name 0 INT1 external interrupt request bit (IT1R) Functions 0 : No interrupt request issued 1 : Interrupt request issued 0 : No interrupt request issued 1 : Interrupt request issued After reset R W 0 0 0 0 0 0 0 R R R R-- R R-- RW 1 2 INT2 external interrupt request bit (IT2R) 0 : No interrupt request issued 1 : Interrupt request issued 3 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5, 6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 7 Fix this bit to "0." : "0" can be set by software, but "1" cannot be set. Serial I/O interrupt request bit (S1R) Fig. 8.3.3 Interrupt Request Register 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 21 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (CRTE) 5 VSYNC interrupt enable bit (VSCE) 6 Multi-master I2C-BUS interface interrupt enable bit (IICE) 7 INT3 external interrupt enable bit (IT3E) Fig. 8.3.4 Interrupt Control Register 1 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 0 RW RW RW RW RW RW RW 0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) 3 Fix this bit to "0." 4 f(XIN)/4096 interrupt enable bit (MSE) 5 to 7 Fix these bits to "0." Fig. 8.3.5 Interrupt Control Register 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 22 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Interrupt input polarity register(RE) [Address 00F916 ] B Name Functions After reset R W 0 0 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 0 0 0 0 R-- RW RW RW RW R-- RW 0 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 1,2 Fix These bits to "0." 3 4 5 6 INT1 polarity switch bit (RE3) INT2 polarity switch bit (RE4) INT3 polarity switch bit (RE5) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 7 Fix this bit to "0." Fig. 8.3.6 Interrupt Input Polarity Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 23 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.4 TIMERS This microcomputer has 4 timers: timers 1 to 4. All timers are 8-bit timers with the 8-bit timer latch. The timer block diagram is shown in Figure 8.4.3. All of the timers count down and their divide ratio is 1/(n+1), where n is the value of timer latch. By writing a count value to the corresponding timer latch (addresses 00F016 to 00F316 : timers 1 to 4), the value is also set to a timer, simultaneously. The count value is decremented by 1. The timer interrupt request bit is set to "1" by a timer overflow at the next count pulse, after the count value reaches "0016." 8.4.1 Timer 1 Timer 1 can select one of the following count sources: * f(XIN)/16 * f(XIN)/4096 The count source of timer 1 is selected by setting bit 0 of timer 12 mode register 1 (address 00F416). Timer interrupt request occurs at timer 1 overflow. At reset, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. The f(XIN)/16 is selected as the timer 3 count source. The internal reset is released by timer 4 overflow in this state and the internal clock is connected. At execution of the STP instruction, timers 3 and 4 are connected by hardware and "FF16" is automatically set in timer 3; "0716" in timer 4. However, the f(XIN)/16 is not selected as the timer 3 count source. So set both bit 0 of timer 34 mode register (address 00F516) and bit 6 at address 00C716 to "0" before execution of the STP instruction (f(XIN)/16 is selected as the timer 3 count source). The internal STP state is released by timer 4 overflow in this state and the internal clock is connected. As a result of the above procedure, the program can start under a stable clock. The timer-related registers is shown in Figures 8.4.1 and 8.4.2. 8.4.2 Timer 2 Timer 2 can select one of the following count sources: * f(XIN)/16 * Timer 1 overflow signal * External clock from the TIM2 pin The count source of timer 2 is selected by setting bits 4 and 1 of timer 12 mode register (address 00F416). When timer 1 overflow signal is a count source for the timer 2, the timer 1 functions as an 8bit prescaler. Timer 2 interrupt request occurs at timer 2 overflow. 8.4.3 Timer 3 Timer 3 can select one of the following count sources: * f(XIN)/16 * External clock from the HSYNC pin * External clock from the TIM3 pin The count source of timer 3 is selected by setting bits 5 and 0 of timer 34 mode register (address 00F516). Timer 3 interrupt request occurs at timer 3 overflow. 8.4.4 Timer 4 Timer 4 can select one of the following count sources: * f(XIN)/16 * f(XIN)/2 * Timer 3 overflow signal The count source of timer 3 is selected by setting bits 1 and 4 of timer 34 mode register (address 00F516). When timer 3 overflow signal is a count source for the timer 4, the timer 3 functions as an 8bit prescaler. Timer 4 interrupt request occurs at timer 4 overflow. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 24 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Timer 12 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Timer mode register (T12M) [Address 00F416] B 0 1 Name Functions After reset R W 0 0 0 0 0 RW RW RW RW RW Timer 1 count source 0: f(XIN)/16 selection bit 1 (T12M0) 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 1: Timer 1 overflow 2 Timer 1 count stop bit (T12M2) 3 Timer 2 count stop bit (T12M3) 4 Timer 2 internal count source selection bit 2 (T12M4) 5 Fix this bit to "0." 0 0 RW R-- 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Fig. 8.4.1 Timer 12 Mode Register Timer 34 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F516] B Name 0 Timer 3 count source selection bit (T34M0) 1 Timer 4 internal interrupt count source selection bit (T34M1) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW 2 Timer 3 count stop bit (T34M2) 3 Timer 4 count stop bit (T34M3) 4 Timer 4 count source selection bit (T34M4) 5 0 0 0 0 RW RW RW RW Timer 3 external count 0: TIM3 pin input source selection bit 1: HSYNC pin input (T34M5) 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Fig. 8.4.2 Timer 34 Mode Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 25 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Data bus 8 1/4096 Timer 1 latch (8) 8 XIN 1/2 1/8 T12M0 T12M2 Timer 1 (8) 8 T12M4 8 Timer 1 interrupt request Timer 2 latch (8) 8 TIM2 T12M1 T12M3 8 Timer 2 (8) Timer 2 interrupt request HSYNC 8 FF16 Reset STP instruction TIM3 T34M5 Timer 3 latch (8) 8 Timer 3 (8) T34M0 T34M2 8 Timer 3 interrupt request Selection gate : Connected to black colored side at reset T34M1 T12M : Timer 12 mode register T34M : Timer 34 mode register Timer 4 latch (8) 8 Timer 4 (8) T34M4 T34M3 8 0716 Timer 4 interrupt request 8 Notes 1: "H" pulse width of external clock inputs TIM2 and TIM3 needs 4 machine cycles or more. 2: When the external clock source is selected, timers 2 and 3 are counted at a rising edge of input signal. 3: In the stop mode or the wait mode, external clock inputs TIM2 and TIM3 cannot be used. Fig. 8.4.3 Timer Block Diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 26 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.5 SERIAL I/O This microcomputer has a built-in serial I/O which can either transmit or receive 8-bit data serially in the clock synchronous mode. The serial I/O block diagram is shown in Figure 8.5.1. The synchronous clock I/O pin (SCLK), data output pin (SOUT), and data input pin (SIN) also functions as port P2. Bit 3 of the serial I/O mode register (address 00DC16) selects whether the synchronous clock is supplied internally or externally (from the SCLK pin). When an internal clock is selected, bits 1 and 0 select whether f(XIN) or f(XCIN) is divided by 4, 16, 32, or 64. To use SIN pin for serial I/O, set the corresponding bit of the port P2 direction register (address 00C516) to "0." The operation of the serial I/O is described below. The operation of the serial I/O differs depending on the clock source; external clock or internal clock. Data bus XIN 1/2 1/2 Frequency divider 1/4 1/8 1/16 SM2 S SM1 SM0 Synchronization circuit Selection gate : Connected to black colored side at reset. SM : Serial I/O mode register P20 latch SCLK SM3 P21 latch SOUT(/IN) SIN SM6 SM5 : LSB SM3 MSB (See note) Serial I/O shift register (8) (Address 00DD16) 8 Serial I/O counter (8) Serial I/O interrupt request Note : When the data is set in the serial I/O register (address 00DD16), the register functions as the serial I/O shift register. Fig. 8.5.1 Serial I/O Block Diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 27 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Internal clock : The serial I/O counter is set to "7" during the write cycle into the serial I/O register (address 00DD16), and the transfer clock goes HIGH forcibly. At each falling edge of the transfer clock after the write cycle, serial data is output from the SOUT pin. Transfer direction can be selected by bit 5 of the serial I/O mode register. At each rising edge of the transfer clock, data is input from the SIN pin and data in the serial I/O register is shifted 1 bit. After the transfer clock has counted 8 times, the serial I/O counter becomes "0" and the transfer clock stops at HIGH. At this time the interrupt request bit is set to "1." External clock : The an external clock is selected as the clock source, the interrupt request is set to "1" after the transfer clock has been counted 8 counts. However, transfer operation does not stop, so the clock should be controlled externally. Use the external clock of 1 MHz or less with a duty cycle of 50%. The serial I/O timing is shown in Figure 8.5.2. When using an external clock for transfer, the external clock must be held at HIGH for initializing the serial I/O counter. When switching between an internal clock and an external clock, do not switch during transfer. Also, be sure to initialize the serial I/O counter after switching. Notes 1: On programming, note that the serial I/O counter is set by writing to the serial I/O register with the bit managing instructions, such as SEB and CLB. 2: When an external clock is used as the synchronous clock, write transmit data to the serial I/O register when the transfer clock input level is HIGH. Synchronous clock Transfer clock Serial I/O register write signal (See note) Serial I/O output SOUT Serial I/O input SIN D0 D1 D2 D3 D4 D5 D6 D7 Interrupt request bit is set to "1" Note : When an internal clock is selected, the SOUT pin is at high-impedance after transfer is completed. Fig. 8.5.2 Serial I/O Timing (for LSB first) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 28 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name b1 b0 Functions 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT 0, 1 Internal synchronous clock selection bits (SM0, SM1) After reset R W 0 RW 2 3 Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3) 0 0 RW RW 4 Fix this bit to "0." 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin. 0 0 0 0 RW RW RW R-- Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Fig. 8.5.3 Serial I/O Mode Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 29 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.5.1 Serial I/O Common Transmission/Reception mode By writing "1" to bit 6 of the serial I/O mode register, signals SIN and SOUT are switched internally to be able to transmit or receive the serial data. Figure 8.5.4 shows signals on serial I/O common transmission/reception mode. Note: When receiving the serial data after writing "FF16" to the serial I/O register. SCLK Clock SOUT "1" Serial I/O shift register (8) SIN "0" SM6 SM : Serial I/O mode register Fig. 8.5.4 Signals on Serial I/O Common Transmission/Reception Mode Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 30 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6 MULTI-MASTER I2C-BUS INTERFACE The multi-master I2C-BUS interface is a serial communications circuit, conforming to the Philips I2C-BUS data transfer format. This interface, offering both arbitration lost detection and a synchronous functions, is useful for the multi-master serial communications. Figure 8.6.1 shows a block diagram of the multi-master I2C-BUS interface and Table 8.6.1 shows multi-master I2C-BUS interface functions. This multi-master I2C-BUS interface consists of the I2C address register, the I2C data shift register, the I2C clock control register, the I2C control register, the I2C status register and other control circuits. Table 8.6.1 Multi-master I2C-BUS Interface Functions Item Function In conformity with Philips I2C-BUS standard: 10-bit addressing format 7-bit addressing format High-speed clock mode Standard clock mode In conformity with Philips I2C-BUS standard: Master transmission Master reception Slave transmission Slave reception 16.1 kHz to 400 kHz (at = 4 MHz) Format Communication mode SCL clock frequency : System clock = f(XIN)/2 Note : We are not responsible for any third party's infringement of patent rights or other rights attributable to the use of the control function (bits 6 and 7 of the I2C control register at address 00DA16) for connections between the I2C-BUS interface and ports (SCL1, SCL2, SDA1, SDA2). b7 I2C address register (S0D) b0 Interrupt generating circuit Interrupt request signal (IICIRQ) SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW Address comparator Serial data (SDA) Noise elimination circuit Data control circuit b7 I C data shift register S0 2 b0 b7 MST TRX BB PIN b0 AL AAS AD0 LRB AL circuit Internal data bus I C status register (S1) 2 BB circuit Serial clock (SCL) Noise elimination circuit Clock control circuit b7 ACK b0 ACK FAST CCR4 CCR3 CCR2 CCR1 CCR0 MODE BIT b7 BSEL1 BSEL0 10BIT SAD ALS b0 ESO BC2 BC1 BC0 I2C clock control register (S2) Clock division I2C control register (S1D) System clock () Bit counter Fig. 8.6.1 Block Diagram of Multi-master I2C-BUS Interface Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 31 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.1 I2C Data Shift Register The I2C data shift register (S0 : address 00D716) is an 8-bit shift register to store receive data and write transmit data. When transmit data is written into this register, it is transferred to the outside from bit 7 in synchronization with the SCL clock, and each time one-bit data is output, the data of this register are shifted one bit to the left. When data is received, it is input to this register from bit 0 in synchronization with the SCL clock, and each time one-bit data is input, the data of this register are shifted one bit to the left. The I2C data shift register is in a write enable status only when the ESO bit of the I2C control register (address 00DA16) is "1." The bit counter is reset by a write instruction to the I2C data shift register. When both the ESO bit and the MST bit of the I2C status register (address 00D916) are "1," the SCL is output by a write instruction to the I2C data shift register. Reading data from the I2C data shift register is always enabled regardless of the ESO bit value. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more. I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0) [Address 00D716] B 0 to 7 Name Functions After reset Indeterminate RW RW D0 to D7 This is an 8-bit shift register to store receive data and write transmit data. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more. Fig. 8.6.2 Data Shift Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 32 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.2 I2C Address Register The I2C address register (address 00D816) consists of a 7-bit slave address and a read/write bit. In the addressing mode, the slave address written in this register is compared with the address data to be received immediately after the START condition are detected. (1) Bit 0: read/write bit (RBW) Not used when comparing addresses, in the 7-bit addressing mode. In the 10-bit addressing mode, the first address data to be received is compared with the contents (SAD6 to SAD0 + RBW) of the I2C address register. The RBW bit is cleared to "0" automatically when the stop condition is detected. (2) Bits 1 to 7: slave address (SAD0-SAD6) These bits store slave addresses. Regardless of the 7-bit addressing mode and the 10-bit addressing mode, the address data transmitted from the master is compared with the contents of these bits. I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00D816] B 0 Name Read/write bit (RBW) Functions After reset R W 0 R-- 1 to 7 Slave address (SAD0 to SAD6) 0 RW Fig. 8.6.3 I2C Address Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 33 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.3 I2C Clock Control Register The I2C clock control register (address 00DB16) is used to set ACK control, SCL mode and SCL frequency. (4) Bit 7: ACK clock bit (ACK) This bit specifies a mode of acknowledgment which is an acknowledgment response of data transmission. When this bit is set to "0," the no ACK clock mode is set. In this case, no ACK clock occurs after data transmission. When the bit is set to "1," the ACK clock mode is set and the master generates an ACK clock upon completion of each 1-byte data transmission.The device for transmitting address data and control data releases the SDA at the occurrence of an ACK clock (make SDA HIGH) and receives the ACK bit generated by the data receiving device. Note: Do not write data into the I2C clock control register during transmission. If data is written during transmission, the I2C clock generator is reset, so that data cannot be transmitted normally. (1) Bits 0 to 4: SCL frequency control bits (CCR0-CCR4) These bits control the SCL frequency. (2) Bit 5: SCL mode specification bit (FAST MODE) This bit specifies the SCL mode. When this bit is set to "0," the standard clock mode is set. When the bit is set to "1," the high-speed clock mode is set. (3) Bit 6: ACK bit (ACK BIT) This bit sets the SDA status when an ACK clock is generated. When this bit is set to "0," the ACK return mode is set and SDA goes to LOW at the occurrence of an ACK clock. When the bit is set to "1," the ACK non-return mode is set. The SDA is held in the HIGH status at the occurrence of an ACK clock. However, when the slave address matches the address data in the reception of address data at ACK BIT = "0," the SDA is automatically made LOW (ACK is returned). If there is a mismatch between the slave address and the address data, the SDA is automatically made HIGH (ACK is not returned). ACK clock: Clock for acknowledgement I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16] B 0 to 4 Name Functions After reset R W 0 SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4-CCR0 mode clock mode 0 0 to 0 2 03 04 05 06 1D 1E 1F ... RW Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3 500/CCR value 1000/CCR value (at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0 RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1 Fig. 8.6.4 I2C Address Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 34 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.4 I2C Control Register The I2C control register (address 00DA16) controls the data communication format. (3) Bit 4: data format selection bit (ALS) This bit decides whether or not to recognize slave addresses. When this bit is set to "0," the addressing format is selected, so that address data is recognized. When a match is found between a slave address and address data as a result of comparison or when a general call (refer to "8.6.5 I2C Status Register," bit 1) is received, transmission processing can be performed. When this bit is set to "1," the free data format is selected, so that slave addresses are not recognized. (1) Bits 0 to 2: bit counter (BC0-BC2) These bits decide the number of bits for the next 1-byte data to be transmitted. An interrupt request signal occurs immediately after the number of bits specified with these bits are transmitted. When a START condition is received, these bits become "0002" and the address data is always transmitted and received in 8 bits. (2) Bit 3: I2C-BUS interface use enable bit (ESO) This bit enables usage of the multimaster I2C BUS interface. When this bit is set to "0," interface is in the disabled status so the SDA and the SCL become high-impedance. When the bit is set to "1," use of the interface is enabled. When ESO = "0," the following is performed. * PIN = "1," BB = "0" and AL = "0" are set (they are bits of the I2C status register at address 00D916 ). * Writing data to the I2C data shift register (address 00D716) is disabled. (4) Bit 5: addressing format selection bit (10BIT SAD) This bit selects a slave address specification format. When this bit is set to "0," the 7-bit addressing format is selected. In this case, only the high-order 7 bits (slave address) of the I2C address register (address 00D816) are compared with address data. When this bit is set to "1," the 10-bit addressing format is selected and all the bits of the I2C address register are compared with the address data. (5) Bits 6 and 7: connection control bits between I 2 C-BUS interface and ports (BSEL0, BSEL1) These bits control the connection between SCL and ports or SDA and ports (refer to Figure 8.6.5). "0" "1" BSEL0 SCL1/P11 SCL Multi-master I2C-BUS interface SDA "0" "1" BSEL1 SCL2/P12 "0" "1" BSEL0 SDA1/P13 "0" "1" BSEL1 SDA2/P14 Note: Set the corresponding direction register to "1" to use the port as multi-master I2C-BUS interface. Fig. 8.6.5 Connection Port Control by BSEL0 and BSEL1 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 35 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16] B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) Fig. 8.6.6 I2C Control Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 36 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.5 I2C Status Register The I2C status register (address 00D916) controls the I2C-BUS interface status. The low-order 4 bits are read-only bits and the highorder 4 bits can be read out and written to. (5) Bit 4: I2C-BUS interface interrupt request bit (PIN) This bit generates an interrupt request signal. Each time 1-byte data is transmitted, the state of the PIN bit changes from "1" to "0." At the same time, an interrupt request signal is sent to the CPU. The PIN bit is set to "0" in synchronization with a falling edge of the last clock (including the ACK clock) of an internal clock and an interrupt request signal occurs in synchronization with a falling edge of the PIN bit. When detecting the STOP condition in slave, the multi-master I2C-BUS interface interrupt request bit (IR) is set to "1" (interrupt request) regardless of falling of PIN bit. When the PIN bit is "0," the SCL is kept in the "0" state and clock generation is disabled. Figure 8.6.8 shows an interrupt request signal generating timing chart. The PIN bit is set to "1" in any one of the following conditions. * Writing "1" to the PIN bit * Executing a write instruction to the I2C data shift register (address 00D716) (See note) * When the ESO bit is "0" * At reset Note: It takes 8 BCLK cycles or more until PIN bit becomes "1" after write instructions are executed to these registers. (1) Bit 0: last receive bit (LRB) This bit stores the last bit value of received data and can also be used for ACK receive confirmation. If ACK is returned when an ACK clock occurs, the LRB bit is set to "0." If ACK is not returned, this bit is set to "1." Except in the ACK mode, the last bit value of received data is input. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00D716). (2) Bit 1: general call detecting flag (AD0) This bit is set to "1" when a general call whose address data is all "0" is received in the slave mode. By a general call of the master device, every slave device receives control data after the general call. The AD0 bit is set to "0" by detecting the STOP condition or START condition. General call: The master transmits the general call address "0016" to all slaves. (3) Bit 2: slave address comparison flag (AAS) This flag indicates a comparison result of address data. In the slave receive mode, when the 7-bit addressing format is selected, this bit is set to "1" in either of the following conditions. * The address data immediately after occurrence of a START condition matches the slave address stored in the high-order 7 bits of the I2C address register (address 00D816). * A general call is received. In the slave reception mode, when the 10-bit addressing format is selected, this bit is set to "1" in the following condition. * When the address data is compared with the I2C address register (8 bits consisting of slave address and RBW), the first bytes match. The state of this bit is changed from "1" to "0" by executing a write instruction to the I2C data shift register (address 00D716). The conditions in which the PIN bit is set to "0" are shown below: * Immediately after completion of 1-byte data transmission (including when arbitration lost is detected) * Immediately after completion of 1-byte data reception * In the slave reception mode, with ALS = "0" and immediately after completion of slave address or general call address reception * In the slave reception mode, with ALS = "1" and immediately after completion of address data reception (6) Bit 5: bus busy flag (BB) This bit indicates the status of the bus system. When this bit is set to "0," this bus system is not busy and a START condition can be generated. When this bit is set to "1," this bus system is busy and the occurrence of a START condition is disabled by the START condition duplication prevention function (See note). This flag can be written by software only in the master transmission mode. In the other modes, this bit is set to "1" by detecting a START condition and set to "0" by detecting a STOP condition. When the ESO bit of the I2C control register (address 00DA16) is "0" at reset, the BB flag is kept in the "0" state. (4) Bit 3: arbitration lost detecting flag (AL) In the master transmission mode, when a device other than the microcomputer sets the SDA to "L,", arbitration is judged to have been lost, so that this bit is set to "1." At the same time, the TRX bit is set to "0," so that immediately after transmission of the byte whose arbitration was lost is completed, the MST bit is set to "0." When arbitration is lost during slave address transmission, the TRX bit is set to "0" and the reception mode is set. Consequently, it becomes possible to receive and recognize its own slave address transmitted by another master device. Arbitration lost: The status in which communication as a master is disabled. (7) Bit 6: communication mode specification bit (transfer direction specification bit: TRX) This bit decides the direction of transfer for data communication. When this bit is "0," the reception mode is selected and the data of a transmitting device is received. When the bit is "1," the transmission mode is selected and address data and control data are output into the SDA in synchronization with the clock generated on the SCL. When the ALS bit of the I2C control register (address 00DA16) is "0" in the slave reception mode, the TRX bit is set to "1" (transmit) if the ___ least significant bit (R/W bit) of the address data transmitted by the ___ master is "1." When the ALS bit is "0" and the R/W bit is "0," the TRX bit is cleared to "0" (receive). The TRX bit is cleared to "0" in one of the following conditions. * When arbitration lost is detected. * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication prevention function (Note). * When MST = "0" and a START condition is detected. * When MST = "0" and ACK non-return is detected. * At reset Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 37 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP (8) Bit 7: Communication mode specification bit (master/slave specification bit: MST) This bit is used for master/slave specification in data communications. When this bit is "0," the slave is specified, so that a START condition and a STOP condition generated by the master are received, and data communication is performed in synchronization with the clock generated by the master. When this bit is "1," the master is specified and a START condition and a STOP condition are generated, and also the clocks required for data communication are generated on the SCL. The MST bit is cleared to "0" in any of the following conditions. * Immediately after completion of 1-byte data transmission when arbitration lost is detected * When a STOP condition is detected. * When occurence of a START condition is disabled by the START condition duplication prevention function (Note). * At reset Note: The START condition duplication prevention function disables the START condition generation, bit counter reset, and SCL output, when the following condition is satisfied: a START condition is set by another master device. I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00D916] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = "0 " 1 : Last bit = "1 " (See note) After reset R W Indeterminate 0 0 R-- R-- R-- R-- RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Fig. 8.6.7 I2C Status Register SCL PIN IICIRQ Fig. 8.6.8 Interrupt Request Signal Generation Timing Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 38 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.6 START Condition Generation Method When the ESO bit of the I2C control register (address 00DA16) is "1," execute a write instruction to the I2C status register (address 00D916) to set the MST, TRX and BB bits to "1." A START condition will then be generated. After that, the bit counter becomes "0002" and an SCL is output for 1 byte . The START condition generation timing and BB bit set timing are different in the standard clock mode and the highspeed clock mode. Refer to Figure 8.6.9 for the START condition generation timing diagram, and Table 8.6.2 for the START condition/ STOP condition generation timing table. I2C status registe write signal SCL SDA BB flag Setup time Setup time Hold time Set time for BB flag Fig. 8.6.9 START Condition Generation Timing Diagram 8.6.7 STOP Condition Generation Method When the ESO bit of the I2C control register (address 00DA16) is "1," execute a write instruction to the I2C status register (address 00D916) to set the MST bit and the TRX bit to "1" and the BB bit to "0". A STOP condition will then be generated. The STOP condition generation timing and the BB flag reset timing are different in the standard clock mode and the high-speed clock mode. Refer to Figure 8.6.10 for the STOP condition generation timing diagram, and Table 8.6.2 for the START condition/STOP condition generation timing table. I2C status register write signal SCL SDA BB flag Setup time Hold time Reset time for BB flag Fig. 8.6.10 STOP Condition Generation Timing Diagram Table 8.6.2 START Condition/STOP Condition Generation Timing Table Item Standard Clock Mode Setup time 5.0 s (20 cycles) (START condition) Setup time 4.25 s (17 cycles) (STOP condition) 5.0 s (20 cycles) Hold time Set/reset time 3.0 s (12 cycles) for BB flag High-speed Clock Mode 2.5 s (10 cycles) 1.75 s (7 cycles) 2.5 s (10 cycles) 1.5 s (6 cycles) Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 39 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.8 START/STOP Condition Detect Conditions The START/STOP condition detect conditions are shown in Figure 8.6.11 and Table 8.6.3. Only when the 3 conditions of Table 8.6.3 are satisfied, a START/STOP condition can be detected. Note: When a STOP condition is detected in the slave mode (MST = 0), an interrupt request signal "IICIRQ" is generated to the CPU. 8.6.9 Address Data Communication There are two address data communication formats, namely, 7-bit addressing format and 10-bit addressing format. The respective address communication formats are described below. (1) 7-bit addressing format To support the 7-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to "0." The first 7-bit address data transmitted from the master is compared with the high-order 7bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, address comparison of the RBW bit of the I2C address register (address 00D816) is not made. For the data transmission format when the 7-bit addressing format is selected, refer to Figure 8.6.12, (1) and (2). SCL release time SCL SDA (START condition) SDA (STOP condition) Setup time Setup time Hold time (2) 10-bit addressing format Hold time To support the 10-bit addressing format, set the 10BIT SAD bit of the I2C control register (address 00DA16) to "1." An address comparison is made between the first-byte address data transmitted from the master and the 7-bit slave address stored in the I2C address register (address 00D816). At the time of this comparison, an address comparison is performed between the RBW bit of the I2C address regis____ ter (address 00D816) and the R/W bit, which is the last bit of the address data transmitted from the master. In the 10-bit addressing ____ mode, the R/W bit not only specifies the direction of communication for control data but is also processed as an address data bit. When the first-byte address data matches the slave address, the AAS bit of the I2C status register (address 00D916) is set to "1." After the second-byte address data is stored into the I2C data shift register (address 00D716), perform an address comparison between the second-byte data and the slave address by software. When the address data of the 2nd byte matches the slave address, set the RBW bit of the I2C address register (address 00D816) to "1" by software. This ____ processing can match the 7-bit slave address and R/W data, which are received after a RESTART condition is detected, with the value of the I2C address register (address 00D816). For the data transmission format when the 10-bit addressing format is selected, refer to Figure 8.6.12, (3) and (4). Fig. 8.6.11 START Condition/STOP Condition Detect Timing Diagram Table 8.6.3 START Condition/STOP Condition Detect Conditions Standard Clock Mode 6.5 s (26 cycles) < SCL release time 3.25 s (13 cycles) < Setup time 3.25 s (13 cycles) < Hold time High-speed Clock Mode 1.0 s (4 cycles) < SCL release time 0.5 s (2 cycles) < Setup time 0.5 s (2 cycles) < Hold time Note: Absolute time at = 4 MHz. The value in parentheses denotes the number of cycles. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 40 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.6.10 Example of Master Transmission An example of master transmission in the standard clock mode, at the SCL frequency of 100 kHz with the ACK return mode enable, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and "0" in the RBW bit. Set the ACK return mode and SCL = 100 kHz by setting "8516" in the I2C clock control register (address 00DB16). Set "1016" in the I2C status register (address 00D916) and hold the SCL at HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00DA16). Set the address data of the destination of transmission in the highorder 7 bits of the I2C data shift register (address 00D716) and set "0" in the least significant bit. Set "F016" in the I2C status register (address 00D916) to generate a START condition. At this time, an SCL for 1 byte and an ACK clock automatically occurs. Set transmit data in the I2C data shift register (address 00D716). At this time, an SCL and an ACK clock automatically occurs. When transmitting control data of more than 1 byte, repeat step . Set "D016" in the I2C status register (address 00D916). After this, if ACK is not returned or transmission ends, a STOP condition will be generated. 8.6.11 Example of Slave Reception An example of slave reception in the high-speed clock mode, at the SCL frequency of 400 kHz, with the ACK non-return mode enabled while using the addressing format, is shown below. Set a slave address in the high-order 7 bits of the I2C address register (address 00D816) and "0" in the RBW bit. Set the ACK non-return mode and SCL = 400 kHz by setting "2516" in the I2C clock control register (address 00DB16). Set "1016" in the I2C status register (address 00D916) and hold the SCL at HIGH. Set a communication enable status by setting "4816" in the I2C control register (address 00DA16). When a START condition is received, an address comparison is executed. *When all transmitted address are"0" (general call): AD0 of the I2C status register (address 00D916) is set to "1" and an interrupt request signal occurs. *When the transmitted addresses match the address set in : ASS of the I2C status register (address 00D916) is set to "1" and an interrupt request signal occurs. *In the cases other than the above: AD0 and AAS of the I2C status register (address 00D916) are set to "0" and no interrupt request signal occurs. Set dummy data in the I2C data shift register (address 00D716). When receiving control data of more than 1 byte, repeat step . When a STOP condition is detected, the communication ends. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 41 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP S Slave address R/W A Data A Data A/A P 7 bits " 0" 1 to 8 bits 1 to 8 bits (1) A master-transmitter transmits data to a slave-receiver S Slave address R/W A Data A Data A P 7 bits " 1" 1 to 8 bits 1 to 8 bits (2) A master-receiver receives data from a slave-transmitter Slave address R/W 1st 7 bits Slave address 2nd byte S A A Data A Data A/A P 1 to 8 bits 7 bits " 0" 8 bits 1 to 8 bits (3) A master-transmitter transmits data to a slave-receiver with a 10-bit address Slave address R/W 1st 7 bits Slave address 2nd byte Slave address R/W 1st 7 bits S A A Sr Data A Data 1 to 8 bits A P 7 bits " 0" 8 bits 7 bits "1" 1 to 8 bits (4) A master-receiver receives data from a slave-transmitter with a 10-bit address S : START condition A : ACK bit Sr : Restart condition P : STOP condition R/W : Read/Write bit From master to slave From slave to master Fig. 8.6.12 Address Data Communication Format 8.6.12 Precautions when using multi-master I2C-BUS interface (1) Read-modify-write instruction Precautions for executing the read-modify-write instructions such as SEB, and CLB, is for each register of the multi-master I2C-BUS interface are described below. *I2C data shift register (S0) When executing the read-modify-write instruction for this register during transfer, data may become an arbitrary value. *I2C address register (S0D) When the read-modify-write instruction is executed for this register at detection of the STOP condition, data may become an arbitrary ______ value. It is because hardware changes the read/write bit (RBW) at the timing. *I2C status register (S1) Do not execute the read-modify-write instruction for this register because all bits of this register are changed by hardware. *I2C control register (S1D) When the read-modify-write instruction is executed for this register at detection of the START condition or at completion the byte transfer, data may become an arbitrary value. Because hardware changes the bit counter (BC0-BC2) at the timing. *I2C clock control register (S2) The read-modify-write instruction can be executed for this register. (2) START condition generation procedure using multi-master Procedure example (The necessary conditions for the procedure are described in to below). * * -- LDA SEI BBS 5,S1,BUSBUSY BUSFREE: STA S0 LDM #$F0, S1 CLI * * BUSBUSY: CLI * * (Take out slave address value) (Interrupt disabled) (BB flag confirmation and branch process) (Write slave address value) (Trigger START condition generation) (Interrupt enabled) (Interrupt enabled) Use "STA," "STX" or "STY" of the zero page addressing instruction for writing the slave address value to the I2C data shift register. Use "LDM" instruction for setting trigger of START condition generation. Write the slave address value of and set trigger of START condition generation as in continuously as shown in the procedure example. Disable interrupts during the following three process steps: * BB flag confirmation * Write of slave address value * Trigger of START condition generation When the condition of the BB flag is bus busy, enable interrupts immediately. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 42 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP (3) RESTART condition generation procedure Procedure example (The necessary conditions for the procedure are described in to below.) Execute the following procedure when the PIN bit is "0." * * #$00, S1 -- S0 #$F0, S1 * * Select the slave receive mode when the PIN bit is "0." Do not write "1" to the PIN bit. Neither "0" nor "1" is specified for the writing to the BB bit. The TRX bit becomes "0" and the SDA pin is released. The SCL pin is released by writing the slave address value to the I2C data shift register. Use "STA," "STX" or "STY" of the zero page addressing instruction for writing. Use "LDM" instruction for setting trigger of RESTART condition generation. Write the slave address value of and set trigger of RESTART condition generation of continuously, as shown in the procedure example. Disable interrupts during the following two process steps: * Write slave address value * Trigger RESTART condition generation (4) STOP condition generation procedure Procedure example (The necessary conditions for the procedure are described in to below.) * * LDM LDA SEI STA LDM CLI (Select slave receive mode) (Take out slave address value) (Interrupt disabled) (Write slave address value) (Trigger RESTART condition generation) (Interrupt enabled) SEI LDM #$C0, S1 NOP LDM #$D0, S1 CLI * * (Interrupt disabled) (Select master transmit mode) (Set NOP) (Trigger STOP condition generation) (Interrupt enabled) Write "0" to the PIN bit when master transmit mode is selected. Execute "NOP" instruction after master transmit mode is set. Also, set trigger of STOP condition generation within 10 cycles after selecting the master trasmit mode. Disable interrupts during the following two process steps: * Select master transmit mode * Trigger STOP condition generation (5) Writing to I2C status register Do not execute an instruction to set the PIN bit to "1" from "0" and an instruction to set the MST and TRX bits to "0" from "1" simultaneously as it may cause the SCL pin the SDA pin to be released after about one machine cycle. Also, do not execute an instruction to set the MST and TRX bits to "0" from "1" when the PIN bit is "1," as it may cause the same problem. (6) Process after STOP condition generation Do not write data in the I2C data shift register S0 and the I2C status register S1 until the bus busy flag BB becomes "0" after generation the STOP condition in the master mode. Doing so may cause the STOP condition waveform from being generated normally. Reading the registers does not cause the same problem. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 43 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.7 PWM OUTPUT FUNCTION This microcomputer is equipped with two 14-bit PWM (DA) and six 8-bit PWMs (PWM0-PWM5). DA1 and DA2 have a 14-bit resolution with the minimum resolution bit width of 0.25 s and a repeat period of 4096 s (for f(XIN) = 8 MHz). PWM0-PWM7 have the same circuit structure and an 8-bit resolution with minimum resolution bit width of 4 s and repeat period of 1024 s (for f(XIN) = 8 MHz). Figure 8.7.1 shows the PWM block diagram. The PWM timing generating circuit applies individual control signals to DA and PWM0- PWM5 using f(XIN) divided by 2 as a reference signal. 8.7.4 Operating of 14-bit PWM As with 8-bit PWM, set the bit 0 of PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. Next, select the output polarity by bit 2 of PWM output control register 2 (address 00D616). Then, the 14-bit PWM outputs from the D-A output pin by setting bit 1 of PWM output control register 1 to "0" (at reset, this bit already set to "0" automatically) to select the DA output. The output example of the 14-bit PWM is shown in Figure 8.7.3. The 14-bit PWM divides the data of the DA latch into the low-order 6 bits and the high-order 8 bits. The fundamental waveform is determined with the high-order 8-bit data "DH." A HIGH area with a length t DH (HIGH area of fundamental waveform) is output every short area of "t" = 256 = 64 s ( is the minimum resolution bit width of 250 ns). The HIGH level area increase interval (tm) is determined with the low-order 6-bit data "DL." The HIGH are of smaller intervals "tm" shown in Table 5 is longer by t than that of other smaller intervals in PWM repeat period "T" = 64t. Thus, a rectangular waveform with the different HIGH width is output from the DA pins. Accordingly, the PWM output changes by unit pulse width by changing the contents of the DA-H and DA-L registers. A length of entirely HIGH cannot be output, i. e. 256/256. 8.7.1 Data Setting When outputting DA, first set the high-order 8 bits to the DA-H register (address 00CE16), then the low-order 6 bits to the DA-L register (address 00CF16). When outputting PWM0-PWM5, set 8-bit output data to the PWMi register (i means 0 to 5; addresses 00D016 to 00D416, 00F616). 8.7.2 Transferring Data from Registers to PWM Circuit Data transfer from the 8-bit PWM register to the 8-bit PWM circuit is executed when writing data to the register. The signal output from the 8-bit PWM output pin corresponds to the contents of this register. Also, data transfer from the DA register (addresses 00CE16 and 00CF16) to the 14-bit PWM circuit is executed at writing data to the DA-L register (address 00CF16). Reading from the DA-H register (address 00CE16) means reading this transferred data. Accordingly, it is possible to confirm the data being output from the DA output pin by reading the DA register. 8.7.5 Output after Reset At reset, the output of ports P00-P05 are in the high-impedance state, and the contents of the PWM register and the PWM circuit are undefined. Note that after reset, the PWM output is undefined until setting the PWM register. 8.7.3 Operating of 8-bit PWM The following explains the PWM operation. First, set bit 0 of PWM output control register 1 (address 00D516) to "0" (at reset, bit 0 is already set to "0" automatically), so that the PWM count source is supplied. PWM0-PWM5 are also used as ports P00-P05, respectively. Set those of the port P0 direction register to "1." And select each output polarity by bit 3 of PWM output control register 2 (address 00D616). Then, set bits 2 to 7 of PWM output control register 1 to "1" (PWM output). The PWM waveform is output from the PWM output pins by setting these registers. Figure 8.7.2 shows the 8-bit PWM timing. One cycle (T) is composed of 256 (28) segments. 8 kinds of pulses, relative to the weight of each bit (bits 0 to 7), are output inside the circuit during 1 cycle. Refer to Figure 8.7.2 (a). The 8-bit PWM outputs a waveform which is the logical sum (OR) of pulses corresponding to the contents of bits 0 to 7 of the 8-bit PWM register. Several examples are shown in Figure 8.7.2 (b). 256 kinds of output (HIGH area: 0/256 to 255/256) are selected by changing the contents of the PWM register. An entirely HIGH selection cannot be output, i.e. 256/256. Table 8.7.1 Relation Between the Low-order 6-bit Data and Highlevel Area Increase Interval Low-order 6 bits of Data Area Longer by than That of Other tm (m = 0 to 63) 000000 000001 000010 000100 001000 010000 100000 LSB Nothing m = 32 m = 16, 48 m = 8, 24, 40, 56 m = 4, 12, 20, 28, 36, 44, 52, 60 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62 m = 1, 3, 5, 7, ................................. 57, 59, 61, 63 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 44 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Fig. 8.7.1 PWM Block Diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 45 of 110 13579 60 70 80 90 10 0 11 0 12 0 13 0 14 0 15 0 16 0 17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 25 5 20 30 40 50 Bit 7 54 58 62 66 70 74 78 82 86 90 94 98 102 106 110 114 118 122 126 130 134 138 142 146 150 154 158 162 166 170 174 178 182 186 190 194 198 202 206 210 214 218 222 226 230 234 238 242 246 250 254 Fig. 8.7.2 PWM Timing 52 60 68 76 84 92 10 0 10 8 11 6 12 4 13 2 14 0 14 8 15 6 16 4 17 2 18 0 18 8 19 6 20 4 21 2 22 0 22 8 23 6 24 4 25 2 56 72 88 10 4 12 0 13 6 15 2 16 8 18 4 20 0 21 6 23 2 24 8 80 11 2 14 4 17 6 20 8 24 0 96 16 0 22 4 64 19 2 12 8 2 6 10 14 18 22 26 30 34 38 42 46 50 Bit 6 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z (a) Pulses showing the weight of each bit T = 256 t PWM output t = 4 s T = 1024 s f(XIN) = 8 MHz (b) Example of 8-bit PWM 4 12 20 28 36 44 Bit 5 8 24 40 Bit 4 16 48 Bit 3 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP page 46 of 110 32 Bit 2 Bit 1 Bit 0 0016 (0) 0116 (1) 1816 (24) FF16 (255) t M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Set "2C16" to DA-H register. Set "2816" to DA-L register. b7 b6 b5 b4 b3 b2 b1 b0 [DA-H 0 0 1 0 1 1 0 0 DH register] At writing of DA-L b13 [DA latch] 0 0 1 0 1 1 0 b6 b5 0 1 0 1 b7 b6 b5 b4 b3 b2 b1 b0 [DA-L register] 1 0 1 0 0 0 DL At writing of DA-L b0 0 0 0 These bits decide HIGH level area of fundamental waveform. HIGH level area of fundamental waveform These bits decide smaller interval "tm" in which HIGH leval area is [HIGH level area of fundamental waveform + ]. = Minimum resolution bit width 0.25 s High-order 8-bit value of DA latch Fundamental waveform 0.25 s44 14-bit ... 03 02 01 00 PWM output 2C 2B 2A 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00 Waveform of smaller interval "tm" specified by low-order 6 bits 0.25 s45 0.25 s 14-bit 2C 2B 2A ... 03 02 01 00 PWM output 8-bit counter FF FE FD ... D6 D5 D4 D3 ... 02 01 00 Fundamental waveform of smaller interval "tm" which is not specified by low-order 6 bits is not changed. 0.25 s44 = 0.25 s 14-bit PWM output t0 Low-order 6-bit output of DA latch Repeat period T = 4096 s t1 t2 t3 t4 t5 t59 t60 t61 t62 t63 Fig. 8.7.3 14-bit PWM Timing (f(XIN) = 8 MHz) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 47 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 0 : DA output 1 DA/PN4 selection bit 1 : PN4 output (PW1) 2 P00/PWM0 output selection bit (PW2) 3 P01/PWM1 output selection bit (PW3) 4 P02/PWM2 output selection bit (PW4) 5 P03/PWM3 output selection bit (PW5) 6 P04/PWM4 output selection bit (PW6) 7 P05/PWM5 output selection bit (PW7) 0: P00 output 1: PWM0 output 0: P01 output 1: PWM1 output 0: P02 output 1: PWM2 output 0: P03 output 1: PWM3 output 0: P04 output 1: PWM4 output 0: P05 output 1: PWM5 output After reset R W RW 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW Fig. 8.7.4 PWM Output Control Register 1 PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D616] B Name Functions After reset R W 0,1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 DA output polarity selection bit (PN2) 3 PWM output polarity selection bit (PN3) 4 DA general-purpose output bit (PN4) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH 0 0 0 0 R-- RW RW RW 5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0." 7 0 R-- Fig. 8.7.5 PWM Output Control Register 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 48 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.8 A-D COMPARATOR A-D comparator consists of a 6-bit D-A converter and a comparator. The A-D comparator block diagram is shown in Figure 8.8.1. The reference voltage "Vref" for D-A conversion is set by bits 0 to 5 of the A-D control register 2 (address 00EF16). The comparison result of the analog input voltage and the reference voltage "Vref" is stored in bit 4 of the A-D control register 1 (address 00EE16). For A-D comparison, set "0" to corresponding bits of the direction register to use ports as analog input pins. Write the data to select analog input pins for bits 0 to 2 of the A-D control register 1 and write the digital value corresponding to Vref to be compared to bits 0 to 5 of the A-D control register 2. The voltage comparison is started by writing to the A-D control register 2, and it is completed after 16 machine cycles (NOP instruction 8). Data bus A-D control register 1 Bits 0 to 2 Comparator control A-D1 A-D2 A-D3 A-D4 A-D5 A-D6 A-D control register 1 Analog signal switch Comparator Bit 4 Bit 5 Bit 4 A-D control register 2 Bit 3 Bit 2 Bit 1 Bit 0 Switch tree Resistor ladder Fig. 8.8.1 A-D Comparator Block Diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 49 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EE16] B 0 to 2 Name Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : Do not set 1 : Do not set After reset R W 0 RW 3 4 5 to 7 This bit is a write disable bit. When this bit is read out, the value is "0." Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate 0 R-- R-- R-- Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are "0." Fig. 8.8.2 A-D Control Register 1 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00EF16] B 0 to 5 Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After re set R W 0 RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R-- 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0." Fig. 8.8.3 A-D Control Register 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 50 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.9 D-A CONVERTER This microcomputer has 2 D-A converters with 6-bit resolution. D-A converter block diagram is shown in Figure 8.9.1. D-A conversion is performed by setting the value in the DA conversion register. The result of D-A conversion is output from the DA pin by setting "1" to the DA output enable bit of the port P3 output mode control register (bits 2 and 3 at address 00CD16). The output analog voltage V is determined with the value n (n: decimal number) in the DA conversion register. V = VCC n 64 (n = 0 to 63) The DA output does not build in a buffer, so connect an external buffer when driving a low-impedance load. Note: Only M37221EASP/FP have a built-in D-A converter. Data bus DA1 conversion register [address 00DE16] 6 Resistor ladder DA1 output enable bit P30/A-D5/DA1 DA2 conversion register [address 00DF16] 6 Resistor ladder DA2 output enable bit P31/A-D6/DA2 Fig. 8.9.1 D-A converter block diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 51 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP P3 output mode control register b7 b6 b5 b4 b3 b2 b1 b0 P3 output mode control register(P3S) [Address 00CD16] B 0 1 2 3 Name P30 output form selection bit (P30S) P31 output form selection bit (P31S) DA1 output enable bit (DA1S) DA2 output enable bit (DA2S) Functions 0: CMOS output 1: N-channel open-drain output 0: CMOS output 1: N-channel open-drain output 0: P30 input/output 1: DA1 output 0: P31 input/output 1: DA2 output After reset R W 0 0 0 0 0 RW RW RW RW R-- 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Fig. 8.9.2 P3 output mode control register DA conversion register i b7 b6 b5 b4 b3 b2 b1 b0 0 DA conversion register i (i=1, 2) (DAi) [Addresses 00DE16, 00DF16] B Name b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 0/64Vcc 1 : 1/64Vcc 0 : 2/64Vcc After reset R W 0 RW 0 DA conversion to selection bit 5 (DAi0 to DAi5) 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 61/64Vcc 0 : 62/64Vcc 1 : 63/64Vcc 6 7 Fix this bit to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 0 RW R-- Note : When use M37221M4H/M6H/M8H/MAH-XXXSP/FP, there is not this register. Fix to " 0016." Fig. 8.9.3 DA conversion register i (i = 1, 2) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 52 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.10 ROM CORRECTION FUNCTION This can correct program data in the ROM. Up to 2 addresses can be corrected ; a program for correction is stored in the ROM correction memory in the RAM as the top address. There are 2 vectors for ROM correction : Vector 1 : address 02C016 Vector 2 : address 02E016 Set the address of the ROM data to be corrected into the ROM correction address register. When the value of the counter matches the ROM data address in the top address of the ROM correction vector, the main program branches to the correction program stored in the ROM memory. To return from the correction program to the main program, the op code and operand of the JMP instruction (total of 3 bytes) are necessary at the end of the correction program. The ROM correction function is controlled by the ROM correction enable register. Notes 1: Specify the first address (op code address) of each instruction as the ROM correction address. 2: Use the JMP instruction (total of 3 bytes) to return from the correction program to the main program. 3: Do not set the same ROM correction address to both vectors 1 and 2. ROM correction address 1 (high-order) 021716 ROM correction address 1 (low-order) 021816 ROM correction address 2 (high-order) 021916 ROM correction address 2 (low-order) 021A16 Fig. 8.10.1 ROM Correction Address Registers ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 ROM correction enable register (RCR) [Address 021B16] B 0 1 Name Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 0 0 RW RW RW R-- 2, 3 Fix these bits to "0." 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Fig. 8.10.2 ROM Correction Enable Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 53 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11 OSD FUNCTIONS Table 8.11.1 outlines the OSD functions. This microcomputer incorporates an OSD control circuit of 24 characters 2 lines. OSD is controlled by the CRT control register. Up to 256 kinds of characters can be displayed. The colors can be specified for each character and up to 4 kinds of colors can be displayed on one screen. A combination of up to 8 colors can be obtained by using each output signal (R, G, and B). Characters are displayed in a 12 16 dots configuration to obtain smooth character patterns (refer to Figure 8.11.1). The following shows the procedure how to display characters on the CRT screen. Write the display character code in OSD RAM. Specify the display color by using the color register. Write the color register in which the display color is set in OSD RAM. Specify the vertical position by using the vertical position register. Specify the character size by using the character size register. Specify the horizontal position by using the horizontal position register. Write the display enable bit to the designated block display flag of the CRT control register. When this is done, the OSD starts according to the input of the VSYNC signal. Table 8.11.1 Features of Each Display Mode Parameter Number of display characters Dot structure Kinds of characters Kinds of character sizes Attribute Character font coloring Character background coloring OSD output Display position Display expansion (multiline display) Functions 24 characters 2 lines 12 16 dots 256 kinds 3 kinds Border (black) 1 screen : 8 kinds (per character unit) 1 screen : 8 kinds (per character unit) R, G, B Horizontal: 64 levels, Vertical: 128 levels Possible Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 54 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP The OSD circuit has an extended display mode. This mode allows multiple lines (3 lines or more) to be displayed on the screen by interrupting the display each time one line is displayed and rewriting data in the block for which display has been terminated by software. Figure 8.11.1 shows the configuration of an OSD character. Figure 8.11.2 shows the block diagram of the OSD circuit. Figure 8.11.3 shows OSD control register. 12 dots 16 dots Fig. 8.11.1 Configuration of OSD Character Display Area Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 55 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Clock for OSD OSC1 OSC2 HSYNC VSYNC Display oscillation circuit Control registers for OSD OSD Control circuit Horizontal position register Vertical position register Character size register Color register OSD control register OSD port control register OSD clock selection register (address 00E016) (addresses 00E116, 00E216) (addresses 00E416) (addresses 00E616 to 00E916) (address 00EA16) (address 00EC16) (address 00ED16) OSD RAM 10 bits 24 characters 2 lines OSD ROM 12 dots 16 dots 256 characters Shift register 12-bit Output circuit Shift register 12-bit R G B OUT1 OUT2 Data bus Fig. 8.11.2 Block Diagram of OSD Circuit Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 56 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (CC) [Address 00EA16] B 0 1 2 3 to 6 7 Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on After reset R W 0 0 0 0 RW RW RW R-- Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." P10/OUT2 pin switch bit (CC7) 0 : P10 1 : OUT2 0 RW Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Fig. 8.11.3 OSD Control Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 57 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.1 Display Position The display positions of characters are specified in units called "blocks." There are 2 blocks : blocks 1 and 2. Up to 24 characters can be displayed in each block (refer to "8.11.3 Memory for OSD"). The display position of each block can be set in both horizontal and vertical directions by software. The display start position in the horizontal direction can be selected for all blocks from 64-step display positions in units of 4TC (TC = OSD oscillation cycle). The display start position in the vertical direction for each block can be selected from 128-step display positions in units of 4 scanning lines. Blocks are displayed in conformance with the following rules: * Block 2 is displayed after the display of block 1 is completed (Figure 8.11.4 (a)). * When the display position of block 1 is overlapped with that of block 2 (Figure 8.11.4 (b)), block 1 is displayed in front. * When another block display position appears while one block is displayed (Figure 8.11.4 (c)),only block 1 is displayed. Similarly, when multiline display, block 1 is displayed after the display of block 2 is completed. HR CV1 Block 1 CV2 Block 2 (a) Example when each block is separated HR CV1 = CV2 Block 1 (Block 2 is not displayed) (b) Example when block 2 overlaps with block 1 HR CV1 CV2 Block 1 Block 2 CV1 Block 1 (second) Not displayed Not displayed (c) Example when block 2 overlaps in process of block 1 Notes 1: CV1 or CV2 indicates the vertical display start position of display block 1 or 2. 2: HR indicates the horizontal display start position of display block 1 or 2. Fig. 8.11.4 Display Position Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 58 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP The vertical display start position is determined by counting the horizontal sync signal (HSYNC). At this time, when VSYNC and HSYNC are positive polarity (negative polarity), the count starts at the rising edge (falling edge) of HSYNC signal after the fixed cycle of the rising edge (falling edge) of VSYNC signal. So the interval from the rising edge (falling edge) of VSYNC signal to the rising edge (falling edge) of HSYNC signal needs enough time (2 machine cycles or more) to avoid jitters. The polarity of HSYNC and VSYNC signals can be select with the OSD port control register (address 00EC16). 8 machine cycles or more VSYNC signal input 0.125 to 0.25 [s] ( at f(XIN) = 8MHz) VSYNC control signal in microcomputer Period of counting HSYNC signal HSYNC signal input 8 machine cycles or more 1 2 3 4 5 (See note 2) Not count When bits 0 and 1 of the OSD port control register (address 00EC16) are set to "1" (negative polarity) Notes 1 : The vertical position is determined by counting falling edge of HSYNC signal after rising edge of VSYNC control signal in the microcomputer. 2 : Do not generate falling edge of HSYNC signal near rising edge of VSYNC control signal in microcomputer to avoid jitter. 3 : The pulse width of VSYNC and HSYNC needs 8 machine cycles or more. Fig. 8.11.5 Supplement Explanation for Display Position Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 59 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP The vertical display start position for each block can be set in 512 steps (where each step is 1TH (TH: HSYNC cycle)) as values "0016" to "7F16" in vertical position register i (i = 1 and 2) (addresses 00E116 and 00E216) The vertical position register i is shown in Figure 8.11.6. Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E1 16, 00E216] B 0 to 6 7 Name Functions After reset RW Vertical display start positions 128 steps (0016 to 7F16) (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Indeterminate R W 0 R-- Fig. 8.11.6 Vertical Position Register i Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 60 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP The horizontal display start position is common to all blocks, and can be set in 64 steps (where 1 step is 4TC, TC being the OSD oscillation cycle) as values "0016" to "3F16" in bits 0 to 5 of the horizontal position register (address 00D116). The horizontal position register is shown in Figure 8.11.7. Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E0 16] B 0 to 5 Name Horizontal display start positions (HR0 to HR5) Functions 64 steps (0016 to 3F16) After reset R W 0 0 RW R-- 6, 7 Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are "0." Fig. 8.11.7 Horizontal Position Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 61 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.2 Character Size The size of characters to be displayed can be from 3 sizes for each block. Use the character size register (address 00E416) to set a character size. The character size of block 1 can be specified by using bits 0 and 1 of the character size register; the character size of block 2 can be specified by using bits 2 and 3. Figure 8.11.8 shows the character size register. The character size can be selected from 3 sizes: minimum size, medium size and large size. Each character size is determined by the number of scanning lines in the height (vertical) direction and the oscillating cycle for display (TC) in the width (horizontal) direction. The minimum size consists of [1 scanning line] [1TC]; the medium size consists of [2 scanning lines] [2TC]; and the large size consists of [3 scanning lines] [3TC]. Table 8.11.2 shows the relation between the set values in the character size register and the character sizes. Character Size Register b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E416] B Name Functions 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. After reset Indeterminate RW RW 0, 1 Character size of block 1 selection bits (CS10, CS11) 2,3 Character size of block 2selection bits (CS20,CS21) 4 to 7 Indeterminate RW Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Fig. 8.11.8 Character Size Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 62 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Minimum Medium Large Horizontal display start position Fig. 8.11.9 Display Start Position of Each Character Size (Horizontal Direction) Table. 8.11.2 Relation between Set Values in Character Size Register and Character Sizes Set values of character size register CSi1 0 0 1 1 CSi0 0 1 0 1 Character Width (horizontal) direction size TC: oscillating cycle for display Minimum Medium Large This is not available 1 TC 2 TC 3 TC Height (vertical) direction scanning lines 1 2 3 Notes 1: The display start position in the horizontal direction is not affected by the character size. In other words, the horizontal display start position is common to all blocks even when the character size varies with each block (refer to Figure 8.11.9). 2: i indicates 1 or 2. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 63 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.3 Clock for OSD The following 2 types of clocks can be selected for OSD display. * Main clock supplied from XIN pin * Main clock supplied from XIN pin divided by I.5 * Clock from the ceramic resonator or the LC or oscillator from the pins OSC1 and OSC2 * Clock from the ceramic resonator or the quartz-crystal oscillator supplied from pins OSC1 and OSC2. The OSD clock for each block can be selected by the OSD clock selection register (address 00ED16). When selecting the main clock, set the oscillation frequency to 8 MHz. OSD Clock Selection Register b7 b6 b5 b4 b3 b2 b1 b0 000000 OSD clock selection register (CK) [Address 00ED16] B Name Functions After reset R W 0 RW 0, 1 OSD clock Functions b1 b0 selection bits 0 0 The clock for display is supplied by connecting RC (CK0,CK1) or LC across the pins OSC1 and OSC2. 0 1 Since the main clock is used as the clock for display, the oscillation frequency is limited. Because of this, the character size in width (horizontal) 0 direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P33 and P34 respectively. 1 OSD oscillation frequency = f(XIN) OSD oscillation frequency = f(XIN)/1.5 1 1 The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. * a ceramic resonator only for OSD * a quartz-crystal oscillator only for OSD and a feedback resistor (See note) 0 RW 2 to 7 Fix these bits to "0." Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator for OSD across the pINs XIN and XOUT. Fig. 8.11.10 OSD clock selection Circuit Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 64 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.4 Memory for OSD There are 2 types of memory for OSD: OSD ROM (addresses 1000016 to 11FFF16) used to store character dot data and OSD RAM (addresses 060016 to 06B716) used to specify the characters and colors to be displayed. (1) OSD ROM (addresses 1000016 to 11FFF16) The dot pattern data for OSD characters is stored in the OSD ROM. To specify the kinds of character font, it is necessary to write the character code (Table 8.11.3) into the OSD RAM. The OSD ROM has a capacity of 8K bytes. Since 32 bytes are required for 1 character data, the ROM can stores up to 256 kinds of characters. The OSD ROM space is broadly divided into 2 areas. The [vertical 16 dots] [horizontal (left side) 8 dots] data of display characters are stored in addresses 1000016 to 107FF16 and 1100016 to 117FF16 ; the [vertical 16 dots] [horizontal (right side) 4 dots] data of display characters are stored in addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 (refer to Figure 8.11.11). Note however that the highorder 4 bits in the data to be written to addresses 1080016 to 10FFF16 and 1180016 to 11FFF16 must be set to "1" (by writing data "FX16"). Data of the character font is specified shown in Figure 8.11.11. 10XX016 or 11XX016 10XXF16 or 11XXF16 b7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 b0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 0 10XX016 +80016 or 11XX016 +80016 10XXF16 +80016 or 11XXF16 +80016 b7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 b3 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fig. 8.11.11 Character Font Data Storing Address Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 65 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Table 8.11.3 Character Code List (Partially Abbreviated) Character code Character data storage address Left 8 dots lines 1000016 to 1000F16 1001016 to 1001F16 1002016 to 1002F16 1003016 to 1003F16 : (2) OSD RAM (addresses 060016 to 06B716) The OSD RAM is allocated at addresses 060016 to 06B716, and is divided into a display character code specification part, and color code specification part for each block. Table 8.11.4 shows the contents of the OSD RAM. For example, to display 1 character position (the left edge) in block 1, write the character code in address 060016, write the color code at 068016. The structure of the OSD RAM is shown in Figure 8.11.12. Right 4 dots lines 1080016 to 1080F16 1081016 to 1081F16 1082016 to 1082F16 1083016 to 1083F16 : 0016 0116 0216 0316 : 7E16 107E016 to 107EF16 107F016 to 107FF16 1100016 to 1100F16 1101016 to 1101F16 : 10FE016 to 10FEF16 10FF016 to 10FFF16 1180016 to 1180F16 1181016 to 1181F16 : 7F16 8016 8116 : FD16 117D016 to 117DF16 117E016 to 117EF16 117F016 to 117FF16 11FD016 to 11FDF16 11FE016 to 11FEF16 11FF016 to 11FFF16 FE16 FF16 Table 8.10.4 Contents of OSD RAM Block Display Position (from left) 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Not used 1st character 2nd character 3rd character : 22nd character 23rd character 24th character Character Code Specification 060016 060116 060216 : 061516 061616 061716 061816 : 061F16 062016 062116 062216 : 063516 063616 063716 Color Specification 068016 068116 068216 : 069516 069616 069716 069816 : 069F16 06A016 06A116 06A216 : 06B516 06B616 06B716 Block 1 Block 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 66 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Block 1 [Character specification] 1st character : 0600 16 to 24th character : 061716 Character code Specify 256 characters ("00 16" to "FF16") [Color specification] 1st character : 0680 16 to 24th character : 069716 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 Block 2 [Character specification] 1st character : 0620 16 to 24th character : 063716 Character code Specify 256 characters ("00 16" to "FF16") [Color specification] 1st character : 06A016 to 24th character : 06B7 16 Color register specification 0 0 : Specifying color register 0 0 1 : Specifying color register 1 1 0 : Specifying color register 2 1 1 : Specifying color register 3 1 0 7 0 1 0 7 0 Fig. 8.11.12 Bit structure of OSD RAM Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 67 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.5 Color Register The color of a displayed character can be specified by setting the color to one of the 4 registers (CO0 to CO3: addresses 00E616 to 00E916) and then specifying that color register with the OSD RAM. There are 3 color outputs; R, G and B. By using a combination of these outputs, it is possible to set 8 colors. However, since only 4 color registers are available, up to 4 colors can be disabled at one time. R, G and B outputs are set by using bits 1 to 3 in the color register. Bit 5 is used to specify whether a character output or blank output. Bits 4, 6 and 7 are used to specify character background color. Figure 8.11.12 shows the color register. Color Register i b7 b6 b5 b4 b3 b2 b1 b0 Color regist er i (COi) (i = 0 to 3) [Addresses 00E616 to 00E916] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 R-- RW RW RW RW RW RW RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." B signal output selection bit (COi1) G signal output selection bit (COi2) R signal output selection bit (COi3) 0: No character is output 1: Character is output 0: No character is output 1: Character is output 0: No character is output 1: Character is output B signal output (background) 0: No background color is output selection bit (COi4) (See note 1) 1: Background color is output OUT1 signal output control bit (COi5) (See notes 1, 2) 0: Character is output 1: Blank is output 0: No background color is output G signal output (background) selection bit (COi6) (See note 1) 1: Background color is output R signal output (background) 0: No background color is output selection bit (COi7) (See note 2) 1: Background color is output Notes 1: When bit 5 ="0" and bit 4 = "1," there is output same as a character or border output from pin OUT1. Do not set bit 5 = "0" and bit 4 = "0." 2: When only bit 7 ="1" and bit 5 "0," there is output from pin OUT2. Fig. 8.11.13 Color Register i Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 68 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Table 8.11.5 Display Example of Character Background Coloring (When Green Is Set for a Character and Blue Is Set for Background Color) Border selection register MD0 Color register i G output B output OUT1 output Character output Green No output (See note 2) Same output as character A Video signal and character color (green) are not mixed. OUT2 output COi7 COi6 COi5 COi4 COi3 COi2 COi1 0 0 0 1 (Note 1) 0 1 0 No output Green 0 1 0 1 0 1 0 No output Same output as Video signal and character color (green) are not mixed. character A Green 0 0 0 1 0 0 1 0 No output Blank output TV image of character background is not displayed. Blank output No output (See note 2) Green 0 0 0 1 1 0 1 0 Background Blank output Blue TV image of character background is not displayed. No output (See note 2) 1 0 1 0 1 0 No output Border output (Black) Border output (Black) Green No output (See note 2) Video signal and character color (green) are not mixed. Green 1 0 0 1 0 0 1 0 No output Blank output Black TV image of character background is not displayed. No output (See note 2) 1 0 0 1 1 0 1 0 Background color - border Border output (Black) Blank output Green No output (See note 2) Blue TV image of character background is not displayed. Notes 1 : When COi5 = "0" and COi4 = "1," there is output same as a character or border output from the OUT1 pin. Do not set COi5 = "0" and COi4 = "0." 2 : When only COi7 = "1" and COi5 = "0," there is output from pin OUT2. 3 : The portion "A" in which character dots are displayed is not mixed with any TV video signal. 4 : The wavy-lined arrows in the Table denote video signals. 5 : i indicates 0 to 3, indicates 0 or 1 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 69 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.6 Border An border of 1 clock (1 dot) equivalent size can be added to a character to be displayed in both horizontal and vertical directions. The border is output from the OUT1 pin. In this case, set bit 5 of a color register to "0" (character is output). Border can be specified in units of block by using the border selection register (address 00E516). Figure 8.11.14 shows the border selection register. Table 8.11.6 shows the relationship between the values set in the border selection register and the character border function. Fig. 8.11.15 Example of Border Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16] B 0 1 2 3 to 7 Name Functions After reset R W Block 1 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD10) 1 : Border output Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 0 R-- Block 2 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD20) 1 : Border output Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Fig. 8.11.14 Border Selection Register Table 8.11.6 Relationship between Set Value in Border Selection Register and Character Border Function Border selection register MDi0 0 Functions Example of output R, G, B output OUT1 output R, G, B output OUT1 output Ordinary 1 Border including character Note: i indicates 1or 2 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 70 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.7 Multiline Display This microcomputer can ordinarily display 2 lines on the CRT screen by displaying 2 blocks at different vertical positions. In addition, it can display up to 16 lines by using OSD interrupts. An OSD interrupt request occurs at the point at which that display of each block has been completed. In other words, when a scanning line reaches the point of the display position (specified by the vertical position registers) of a certain block, the character display of that block starts, and an interrupt occurs at the point at which the scanning line exceeds the block. Note: An OSD interrupt does not occur at the end of display when the block is not displayed. In other words, if a block is set to display off by the display control bit of the OSD control register (address 00EA16), an OSD interrupt request does not occur (refer to Figure 8.11.16). Block 1 (on display) Block 2 (on display) Block 1' (on display) Block 2' (on display) "OSD interrupt request" "OSD interrupt request" "OSD interrupt request" "OSD interrupt request" Block 1 (on display) Block 2 (on display) Block 1' (off display) Block 2' (off display) "OSD interrupt request" "OSD interrupt request" No "OSD interrupt request" No "OSD interrupt request" On display (OSD interrupt request occurs at the end of block display) Off display (OSD interrupt request does not occur at the end of block display) Fig. 8.11.16 Note on Occurence of OSD Interrupt Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 71 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.8 OSD Output Pin Control The OSD output pins R, G, B and OUT1 can also function as ports P52-P55. Set the corresponding bit of the port P5 direction register (address 00CB16) to "0" to specify these pins as OSD output pins, or to "1" to specify as the general-purpose port P5. The OUT2 can also function as port P10. Set bit 0 of the OSD port control register (address 00EC16) to "1" (output mode). After that, set bit 7 of the OSD control register to "1" to specify the pin as OSD output pin, or set it to "0" to specify as port P10. The input polarity of the HSYNC and VSYNC, and the output polarity of signals R, G, B, OUT1 and OUT2 can be specified with the OSD port control register (address 00EC). Set bits to "0" to specify positive polarity; set it to "1" to specify negative polarity (refer to Figure 8.11.13). The OSD port control register is shown in Figure 8.11.17. OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (CRTP) [Address 00EC16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (R/G/B) OUT2 output polarity switch bit (OUT2) OUT1 output polarity switch bit (OUT1) R signal output switch bit (OP5) G signal output switch bit(OP6) B signal output switch bit(OP7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : R signal output 1 : MUT E signal output 0 : G signal output 1 : MUTE signal output 0 : B signal output 1 : MUT E signal output Fig. 8.11.17 OSD Port Control Register Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 72 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.11.9 Raster Coloring Function An entire screen (raster) can be colored by setting CRT port control register. Since each of the R, G and B pins can be switched to raster coloring output, 8 raster colors can be obtained. When the character color/character background color overlaps with the raster color, the color (R, G, B, OUT1, OUT2), specified for the character color/character background color, takes priority over the raster color. This ensures that character color/character background color is not mixed with the raster color. An example of raster coloring is shown in Figure 8.11.18. : Character color "RED" (R + OUT1 + OUT2) : Border color "BLACK" (OUT1 + OUT2) : Background color "MAGENTA" (R + B + OUT1 + OUT2) : Raster color "BLUE" (B + OUT1 + OUT2) A A' HSYNC OUT1 OUT2 R G B Signals across A-A' Fig. 8.11.18 Example of Raster Coloring Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 73 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.12 SOFTWARE RUNAWAY DETECT FUNCTION This microcomputer has a function to decode undefined instructions to detect a software runaway. When an undefined op-code is input to the CPU as an instruction code during operation, the following processing is done. The CPU generates an undefined instruction decoding signal. The device is internally reset due to the undefined instruction decoding signal. As a result of internal reset, the same reset processing as in the case of ordinary reset operation is done, and the program restarts from the reset vector. Note, however, that the software runaway detecting function cannot be disabled. SYNC Address PC ? 01,S 01,S-1 01,S-2 FFFE16 FFFF16 ADH, ADL Data ? PCH PCL PS Reset sequence ADL ADH Undefined instruction decoding signal occurs.Internal reset signal occurs. ? : Undefined instruction decode : Invalid PC : Program counter S : Stack pointer ADL, ADH: Jump destination address of reset Fig. 8.12.1 Sequence at Detecting Software Runaway Detection Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 74 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.13. RESET CIRCUIT When the oscillation of a quartz-crystal oscillator or a ceramic resonator is stable and the power source voltage is 5 V 10 %, hold the RESET pin at LOW for 2 s or more, then return to HIGH. Then, as shown in Figure 8.13.2, reset is released and the program starts from the address formed by using the content of address FFFF16 as the high-order address and the content of the address FFFE16 as the low-order address. The internal states of the microcomputer at reset are shown in Figures 8.2.3 to 8.2.6. An example of the reset circuit is shown in Figure 8.13.1. The reset input voltage must be kept 0.6 V or less until the power source voltage surpasses 4.5 V. Poweron 4 .5 V Power source voltage 0 V Reset input voltage 0 V 0 .6 V Vcc 1 5 M51 953AL RESET 4 3 0.1 F Vss Microcomputer Fig. 8.13.1 Example of Reset Circuit XIN RESET Internal RESET SYNC Address Data ? ? 32768 count of XIN clock cycle (See note 3) ? ? 01, S 01, S-1 01, S-2 FFFE FFFF ADH, ADL Reset address from the vector table ? ? ? ADL ADH Notes 1 : f(XIN) and f() are in the relation : f(XIN) = 2*f (). 2 : A question mark (?) indicates an undefined state that depends on the previous state. 3 : Immediately after a reset, timer 3 and timer 4 are connected by hardware. At this time, "FF16" is set in timer 3 and "0716" is set to timer 4. Timer 3 counts down with f(XIN)/16, and reset state is released by the timer 4 overflow signal. Fig. 8.13.2 Reset Sequence Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 75 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.14 CLOCK GENERATING CIRCUIT The built-in clock generating circuit is shown in Figure 8.13.3. When the STP instruction is executed, the internal clock stops at HIGH. At the same time, timers 3 and 4 are connected by hardware and "FF16" is set in timer 3 and "0716" is set in the timer 4. Select f(XIN)/16 as the timer 3 count source (set bit 0 of the timer mode register 2 to "0" before the execution of the STP instruction). Moreover, set the timer 3 and timer 4 interrupt enable bits to disabled ("0") before execution of the STP instruction). The oscillator restarts when external interrupt is accepted. However, the internal clock keeps its HIGH until timer 4 overflows, allowing time for oscillation stabilization when a ceramic resonator or a quartz-crystal oscillator is used. When the WIT instruction is executed, the internal clock stops in the HIGH but the oscillator continues running. This wait state is released when an interrupt is accepted (See note). Since the oscillator does not stop, the next instruction can be executed at once. When returning from the stop or the wait state, to accept an interrupt, set the corresponding interrupt enable bit to "1" before executing the STP or the WIT instructions. Note: In the wait mode, the following interrupts are invalid. * VSYNC interrupt * OSD interrupt * Timer 2 interrupt using external clock input from TIM2 pin as count source * Timer 3 interrupt using external clock input from TIM3 pin as count source * Timer 4 interrupt using f(XIN)/2 as count source * Timer 1 interrupt using f(XIN)/4096 as count source * f(XIN)/4096 interrupt * Multi-master I2C-BUS interface interrupt Microcomputer XIN XOUT CIN COUT Fig. 8.14.1 Ceramic Resonator Circuit Example Microcomputer XIN Vcc External oscillation circuit Vss Fig. 8.14.2 External Clock Input Circuit Example A circuit example using a ceramic resonator (or a quartz-crystal oscillator) is shown in Figure 8.14.1. Use the circuit constants in accordance with the resonator manufacture's recommended values. A circuit example with external clock input is shown in Figure 8.14.2. Input the clock to the XIN pin, and open the XOUT pin. Interrupt request S Interrupt disable flag I Reset WIT instruction Q Q S Reset S Q R R Selection gate : Connected to black side at reset. T34M : Timer 34 mode register STP instruction R STP instruction Internal clock 1/2 1/8 T34M0 T34M2 Timer 3 Timer 4 XIN XOUT Fig. 8.14.3 Clock Generating Circuit Block Diagram Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 76 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 8.15 DISPLAY OSCILLATION CIRCUIT The OSD oscillation circuit has a built-in clock oscillation circuits, so that a clock for OSD can be obtained simply by connecting an LC, an RC, a ceramic resonator, or a quartz-crystal oscillator across the pins OSC1 and OSC2. Which of the sub-clock or the OSD oscillation circuit is selected by setting bits 0 and 1 of the OSD clock selection register (address 00ED16). 8.17 ADDRESSING MODE The memory access is reinforced with 17 kinds of addressing modes. Refer to SERIES 740 8.18 MACHINE INSTRUCTIONS There are 71 machine instructions. Refer to SERIES 740 9. TECHNICAL NOTES * The divide ratio of the timer is 1/(n+1). * Even though the BBC and BBS instructions are executed immediately after the interrupt request bits are modified (by the program), those instructions are only valid for the contents before the modification. At least one instruction cycle is needed (such as an NOP) between the modification of the interrupt request bits and the execution of the BBC and BBS instructions. * After the ADC and SBC instructions are executed (in the decimal mode), one instruction cycle (such as an NOP) is needed before the SEC, CLC, or CLD instruction is executed. * An NOP instruction is needed immediately after the execution of a PLP instruction. * In order to avoid noise and latch-up, connect a bypass capacitor ( 0.1F) directly between the VCC pin-VSS pin and the VCC pin- CNVSS pin, using a thick wire. * [Electric Characteristic Differences Between Mask ROM and One Time PROM Version MCUs] There are differences in electric characteristics, operation margin, noise immunity, and noise radiation between Mask ROM and One Time PROM version MCUs due to the difference in the manufacturing processes. When manufacturing an application system with the One time PROM version and then switching to use of the Mask ROM version, please perform sufficient evaluations for the commercial samples of the Mask ROM version. OSC1 OSC2 L C1 C2 Fig. 8.15.1 Display Oscillation Circuit 8.16 AUTO-CLEAR CIRCUIT When a power source is supplied, the auto-clear function will operate by connecting the following circuit to the RESET pin. Circuit example 1 Vcc RESET Vss Circuit example 2 RESET Vcc Vss Note : Make the level change from "L" to "H" at the point at which the power source voltage exceeds the specified voltage. Fig. 8.16.1 Auto-clear Circuit Example Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 77 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 10. ABSOLUTE MAXIMUM RATINGS Symbol VCC VI VI Input voltage Input voltage Parameter Power source voltage VCC CNVSS P00-P07,P10-P17, P20-P27, P30-P34, OSC1, XIN, HSYNC, VSYNC, RESET P00-P07, P10-P17, P20-P27, P30-P32, R, G, B, OUT1, D-A, XOUT, OSC2 R, G, B, OUT1, P10-P17, P20-P27, P30, P31, D-A R, G, B, OUT1, P00-P07, P10, P15-P17, P20-P23, P30-P32, D-A P11-P14 P24-P27 Ta = 25 C Conditions All voltages are based on VSS. Output transistors are cut off. Ratings -0.3 to 6 -0.3 to 6 -0.3 to VCC + 0.3 Unit V V V VO Output voltage -0.3 to VCC + 0.3 V IOH IOL1 Circuit current Circuit current 0 to 1 (Note 1) 0 to 2 (Note 2) mA mA IOL2 IOL3 Pd Topr Tstg Circuit current Circuit current Power dissipation Operating temperature Storage temperature 0 to 6 (Note 2) 0 to 10 (Note 3) 550 -10 to 70 -40 to 125 mA mA mW C C 11. RECOMMENDED OPERATING CONDITIONS (Ta = -10 C to 70 C, VCC = 5 V 10 %, unless otherwise noted) Symbol VCC VSS VIH1 Parameter Power source voltage (Note 4), During CPU, CRT operation Power source voltage "H" input voltage P00-P07,P10-P17, P20-P27, P30-P34, SIN, SCLK, HSYNC, VSYNC, RESET, XIN, OSC1, TIM2, TIM3, INT1, INT2, INT3 "H" input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) "L" input voltage P00-P07,P10-P17, P20-P27, P30-P34 "L" input voltage SCL1, SCL2, SDA1, SDA2 (When using I2C-BUS) "L" input voltage HSYNC, VSYNC, RESET,TIM2, TIM3, INT1, INT2, INT3, XIN, OSC1, SIN, SCLK "H" average output current (Note 1) R, G, B, OUT1, D-A, P10-P17, P20-P27, P30, P31 "L" average output current (Note 2) R, G, B, OUT1, D-A, P00-P07, P10, P15-P17, P20-P27, P30-P32 "L" average output current (Note 2) P11-P14 "L" average output current (Note 3) P24-P27 Oscillation frequency (for CPU operation) (Note 5) XIN Oscillation frequency (for CRT display) (Note 5) OSC1 Input frequency TIM2, TIM3 Input frequency SCLK Input frequency SCL1, SCL2 Limits Typ. 5.0 0 Unit V V V Min. 4.5 0 0.8VCC Max. 5.5 0 VCC VIH2 VIL1 VIL2 VIL3 IOH IOL1 IOL2 IOL3 fCPU fCRT fhs1 fhs2 fhs3 0.7VCC 0 0 0 VCC 0.4 VCC 0.3 VCC 0.2 VCC 1 2 6 10 8.1 8.0 100 1 400 V V V V mA mA mA mA MHz MHz kHz MHz kHz 7.9 5.0 8.0 Notes 1: The total current that flows out of the IC must be 20 mA (max.). 2: The total input current to IC (IOL1 + IOL2) must be 30 mA or less. 3: The total average input current for ports P24-P27 to IC must be 20 mA or less. 4: Connect 0.1 F or more capacitor externally across the power source pins VCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally across the pins VCC-CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 78 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 12. ELECTRIC CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = -10 C to 70 C, unless otherwise noted) Symbol ICC Parameter Power source current System operation Test conditions VCC = 5.5 V, f(XIN) = 8 MHz OSD OFF OSD ON Stop mode R, G, B, OUT1, D-A, P10-P17 P20-P27, P30, P31 R, G, B, OUT1, D-A, P00-P07, P10, P15-P17, P20-P23, P30-P32 P11-P14 P11-P14 ______ Min. Limits Typ. Max. 20 40 30 60 300 Unit mA Test circuit 1 VOH VOL "H" output voltage "L" output voltage VCC = 5.5 V, f(XIN) = 0 VCC = 4.5 V IOH = -0.5 mA VCC = 4.5 V IOL = 0.5 mA VCC = 4.5 V VCC = 4.5 V IOL = 10.0 mA VCC = 5.0 V VCC = 5.0 V IOL = 3 mA IOL = 6 mA 2.4 0.4 A V V 2 "L" output voltage "L" output voltage VT+ - VT- Hysteresis Hysteresis (Note) 0.4 0.6 3.0 0.5 0.5 0.7 1.3 V IIZH IIZL RBS "H" input leak current "L" input leak current RESET HSYNC, VSYNC, TIM2, TIM3, INT1-INT3, SCL1, SCL2, SDA1, SDA2, SIN, SCLK ______ RESET, P00-P07, P10-P17, P20-P27, P30-P37, HSYNC, VSYNC ______ RESET, P00-P07, P10-P17, P20-P27, P30-P37, HSYNC, VSYNC 3 VCC = 5.5 V VI = 5.5 V VCC = 5.5 V VI = 0 V VCC = 4.5 V 5 5 130 A A 4 I2C-BUS*BUS switch connection resistor (between SCL1 and SCL2, SDA1 and SDA2) 5 Notes 1: The total current that flows out of the IC must be 20 mA or less. 2: The total input current to IC (IOL1 + IOL2) must be 30 mA or less. 3: The total average input current for ports P24-P27 to IC must be 20 mA or less. 4: Connect 0.1 F or more capacitor externally between the power source pins VCC-VSS so as to reduce power source noise. Also connect 0.1 F or more capacitor externally between the pins VCC-CNVSS. 5: Use a quartz-crystal oscillator or a ceramic resonator for the CPU oscillation circuit. When using the data slicer, use 8 MHz. 6: P06, P07, P15, P23, P24 have hysteresis when used as interrupt input pins or timer input pins. P11-P14 have hysteresis when these pins are used as multimaster I2C-BUS interface ports. P20-P22 have the hysteresis when used as serial I/O pins. 7: Pin names in each parameter are described as below. (1) Dedicated pins: dedicated pin names. (2) Double-/triple-function ports * Same limits: I/O port name. * Function other than parts vary from I/O port limits: function pin name. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 79 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP + Power source voltage 1 A Icc XIN 8.00 MHz OSC1 XOUT Vcc 2 4.5 V Vcc Each output pin OSC2 VOH Vss V or VOL IOH or IOL Vss Pin VCC is made the operation state and is measured the current, with a ceramic resonator. After setting each output pin to HIGH level when measuring VOH and to LOW level when measuring VOL, each pin is measured. 3 5.0 V 4 5.5 V Vcc Vcc IIZH or IIZL A Each input pin Each input pin Vss Vss 5 4.5V Vcc SCL1 or SDA1 IBS A RB S SCL2 or SDA2 Vss VBS RBS = VBS/IBS Fig.12.1 Measurement Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 80 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 13. A-D COMPARISON CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 C to 70 C, unless otherwise noted) Symbol -- -- Resolution Absolute accuracy Parameter Test conditions Limits Min. 0 Typ. 1 Max. 6 2 Unit bits LSB 14. D-A CONVERSION CHARACTERISTICS (VCC = 5 V 10 %, VSS = 0 V, f(XIN) = 8 MHz, Ta = 10 C to 70 C, unless otherwise noted) Symbol Parameter Test conditions Min. Limits Typ. Max. 6 2 3 4 Unit bits LSB s k -- Resolution -- Absolute accuracy tsu Setting time Ro Output resistor Note: Only M37221EASP/FP have a built-in D-A converter. 1 2.5 15. MULTI-MASTER I2C-BUS BUS LINE CHARACTERISTICS Symbol tBUF tHD; STA tLOW tR tHD; DAT tHIGH tF tSU; DAT tSU; STA tSU; STO Parameter Bus free time Hold time for START condition LOW period of SCL clock Rising time of both SCL and SDA signals Data hold time HIGH period of SCL clock Falling time of both SCL and SDA signals Data set-up time Set-up time for repeated START condition Set-up time for STOP condition Standard clock mode High-speed clock mode Unit Min. Max. Min. Max. 4.7 1.3 s 4.0 0.6 s 4.7 1.3 s 1000 20+0.1Cb 300 ns 0 0 0.9 s 4.0 0.6 s 300 20+0.1Cb 300 ns 250 100 ns 4.7 0.6 s 4.0 0.6 s Note: Cb = total capacitance of 1 bus line SDA tHD;STA tSU;STO tBUF tLOW P SCL S tR tF Sr P tHD;STA tHD;DAT tHIGH tSU;DAT tSU;STA S : Start condition Sr : Restart condition P : Stop condition Fig.15.1 Definition Diagram of Timing on Multi-master I2C-BUS Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 81 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 16. PROM PROGRAMMING METHOD The built-in PROM of the One Time PROM version (blank) and the built-in EPROM version can be read or programmed with a generalpurpose PROM programmer using a special programming adapter. Product M37221EASP M37221EAFP Name of Programming Adapter PCA7408 PCA7439 The PROM of the One Time PROM version (blank) is not tested or screened in the assembly process nor any following processes. To ensure proper operation after programming, the procedure shown in Figure 16.1 is recommended to verify programming. Programming with PROM programmer Screening (Caution) (150C for 40 hours) Verification with PROM programmer Functional check in target device Caution : The screening temperature is far higher than the storage temperature. Never expose to 150C exceeding 100 hours. Fig. 16.1 Programming and Testing of One Time PROM Version Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 82 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 17. DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM product: * Mask ROM Order Confirmation Form * Mark Specification Form * Data to be written to ROM, in EPROM form (32-pin DIP Type 27C101, three identical copies) or FDK Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 83 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 18. ONE TIME PROM VERSION M37221EASP/FP MARKING M37221EASP XXXXXX XXXXXX is lot number M37221EAFP XXXXXX XXXXXX is lot number Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 84 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 19. APPENDIX Pin Configuration (TOP VIEW) HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC Outline 42P4B M37221M4H/M6H/M8H/MAH-XXXSP P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 1 2 3 4 42 41 40 39 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 M37221M4H/M6H/M8H/MAH-XXXFP 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5 P31/A-D6 RESET OSC1/P33 OSC2/P34 VCC 23 22 Outline 42P2R-A/E Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 85 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP HSYNC VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34 VCC M37221EASP 9 10 11 12 13 14 15 16 17 18 19 20 21 34 33 32 31 30 29 28 27 26 25 24 23 22 Outline 42P4B P50/HSYNC P51/VSYNC P00/PWM0 P01/PWM1 P02/PWM2 P03/PWM3 P04/PWM4 P05/PWM5 P06/INT2/A-D4 P07/INT1 P23/TIM3 P24/TIM2 P25 P26 P27 D-A P32 CNVSS XIN XOUT VSS 1 2 3 4 5 6 7 8 42 41 40 39 38 37 36 35 P52/R P53/G P54/B P55/OUT1 P20/SCLK P21/SOUT P22/SIN P10/OUT2 P11/SCL1 P12/SCL2 P13/SDA1 P14/SDA2 P15/A-D1/INT3 M37221EAFP 9 10 11 12 13 14 15 16 17 18 19 20 21 34 33 32 31 30 29 28 27 26 25 24 23 22 P16/A-D2 P17/A-D3 P30/A-D5/DA1 P31/A-D6/DA2 RESET OSC1/P33 OSC2/P34 VCC Outline 42P2R-A/E Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 86 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Memory Map M37221M4 H/M6H -XXXSP/FP 000016 Zero page M37221M6HXXXSP/FP RAM (448 bytes) M37221M4HXXXSP/FP RAM (384 bytes) 00C016 SFR area 00FF16 017F16 01BF16 02C016 02E016 02FF16 OSD RAM (96 bytes) (See note) 060016 06B716 Not used M37221M6HXXXSP/FP ROM (24K bytes) A00016 C00016 OSD ROM (8K bytes) 1000016 11FFF16 Not used ROM correction function Vector 1: address 02C016 Vector 2: address 02E016 Not used Not used M37221M4HXXXSP/FP ROM (16K bytes) FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.4 OSD RAM. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 87 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP M37221M8H/MAH-XXXSP/FP, M37221EASP/FP 000016 Zero page 00C016 SFR area 00FF16 M37221MAHXXXSP/FP, M37221EASP/FP RAM (704 bytes) M37221M8HXXXSP/FP RAM (576 bytes) 01FF16 Not used 021716 021B16 02C016 02E016 02FF16 030016 033F16 03BF16 Not used OSD RAM (96 bytes) (See note) M37221MAHXXXSP/FP, M37221EASP/FP RAM (40K bytes) M37221M8HXXXSP/FP RAM (32K bytes) 060016 06B716 Not used 600016 800016 2 page register Not used ROM correction function Vector 1: address 02C016 Vector 2: address 02E016 1000016 OSD ROM (8K bytes) 11FFF16 Not used FF0016 FFDE16 FFFF16 Interrupt vector area Special page 1FFFF16 Note: Refer to Table 8.11.4 OSD RAM. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 88 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Memory Map of Special Function Register (SFR) SFR area (addresses C016 to DF16) Name State immediately after reset> 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address C016 C116 C216 C316 C416 C516 C616 C716 C816 C916 CA16 CB16 CC16 CD16 CE16 CF16 D016 D116 D216 D316 D416 D516 D616 D716 D816 D916 DA16 DB16 DC16 DD16 DE16 DF16 Register Bit allocation b7 State immediately after reset b0 b7 b0 Port P0 (P0) Port P0 direction register (D0) Port P1 (P1) Port P1 direction register (D1) Port P2 (P2) Port P2 direction register (D2) Port P3 (P3) Port P3 direction register (D3) 0 0 0 Port P5 (P5) Port P5 direction register (D5) Port P3 output mode control register (P3S) (Note 1) DA-H register (DA-H) DA-L register (DA-L) PWM0 register (PWM0) PWM1 register (PWM1) PWM2 register (PWM2) PWM3 register (PWM3) PWM4 register (PWM4) PWM output control register 1 (PW) PWM output control register 2 (PN) I2 C data shift register (S0) I2 C address register (S0D) I2 C status register (S1) I2 C control register (S1D) I2 C clock control register (S2) Serial I/O mode register (SM) Serial I/O regsiter (SIO) DA1 conversion register (DA1) (Note 2) DA2 conversion register (DA2) (Note 2) PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0 PN4 PN3 PN2 DA2S DA1S P31S P30S 0 0 ? 0 0 ? SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW MST TRX BB BSEL1 BSEL0 10BIT SAD PIN AL AAS AD0 LRB ALS ES0 BC2 BC1 BC0 0 0 0 FAST ACK ACK MODE CCR4 CCR3 CCR2 CCR1 CCR0 BIT SM6 SM5 0 SM3 SM2 SM1 SM0 0 0 DA15 DA14 DA13 DA12 DA11 DA10 DA25 DA24 DA23 DA22 DA21 DA20 0 0 0 0 ? ? ? 0016 ? 0016 ? 0016 ?? 0016 ? ? ?? 0016 ? 0016 ? ?? ? ? ? ? ? 0016 0016 ? 0016 10 0016 0016 0016 ? ?? ?? ? ? ? ? ? ? ? ? ? 0 0 ? ? ? ? ? ? ? Note 1: As for M37221M4H/M6H/M8H/MAH-XXXSP/FP, fix bits 2 and 3 to "0." 2: M37221M4H/M6H/M8H/MAH-XXXSP/FP do not have this register. Fix this register to "0016." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 89 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP SFR area (addresses E016 to FF16) Name Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address E016 E116 E216 E316 E416 E516 E616 E716 E816 E916 EA16 EB16 EC16 ED16 EE16 EF16 F016 F116 F216 F316 F416 F516 F616 F716 F816 F916 FA16 FB16 FC16 FD16 FE16 FF16 Register b7 Bit allocation b0 b7 HR5 HR4 HR3 HR2 HR1 HR0 CV16 CV15 CV14 CV13 CV12 CV11 CV10 CV26 CV25 CV24 CV23 CV22 CV21 CV20 State immediately after reset b0 Horizontal register (HR) Vertical register 1 (CV1) Vertical register 2 (CV2) Character size register (CS) Border selection register (MD) Color register 0 (CO0) Color register 1 (CO1) Color register 2 (CO2) Color register 3 (CO3) OSD control register (CC) OSD port control register (CRTP) OSD clock selection register (CK) A-D control register 1 (AD1) A-D control register 2 (AD2) Timer 1 (TM1) Timer 2 (TM2) Timer 3 (TM3) Timer 4 (TM4) Timer 12 mode register (T12M) Timer 34 mode register (T34M) PWM5 register (PWM5) 0 0 0 0 ? ? 0 0 ? ? 0 0 CS21 CS20 CS11 CS10 MD20 CO07 CO06 CO05 CO04 CO03 CO02 CO01 CO17 CO16 CO15 CO14 CO13 CO12 CO11 CO27 CO26 CO25 CO24 CO23 CO22 CO21 CO37 CO36 CO35 CO34 CO33 CO32 CO31 MD10 CC7 CC2 CC1 CC0 OP7 OP6 OP5 OUT1 OUT2 R/G/B VSYC HSYC 0 0 0 0 ADM4 0 0 CK1 CK0 ADM2 ADM1 ADM0 0 0 0 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 0 T12M4 T12M3 T12M2 T12M1 T12M0 T34M5 T34M4 T34M3 T34M2 T34M1 T34M0 Interrupt input polarity register (RE) Test register (TEST) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 0 1 IT3R RE5 RE4 RE3 CK0 0 CM2 0 0 0 0 1 0 1 0 1 1 1 0016 11 MSR CK0 IICR VSCR CRTR TM4R TM3R TM2R TM1R 0 0 0 0 S1R 1T2R 1T1R IT3E IICE VSCE CRTE TM4E TM3E TM2E TM1E MSE 0 S1E 1T2E 1T1E 0016 ?? ?? ? 0? 00 0016 0016 0016 0016 0016 ? 0016 0016 ?0 0016 FF16 0716 FF16 0716 0016 0016 ? ? ? CK0 0 0 0016 11 0016 0016 0016 0016 ? ? ? ? ? ? ? 0 ? ? ? ? 0 0 0 0 1 0 0 ? 0 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 90 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 2 page register area (addresses 21716 to 21B16) Name State immediately after reset> 0 : "0" immediately after reset 1 : "1" immediately after reset ? : Indeterminate immediately after reset Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Address 21716 21816 21916 21A16 21B16 Register ROM correction address 1 (high-order) ROM correction address 1 (low-order) ROM correction address 2 (high-order) ROM correction address 2 (low-order) ROM correction enable register (RCR) Bit allocation b7 State immediately after reset b 0 b7 b0 0 0 RCR1 RCR0 0016 0016 0016 0016 0016 Note: Only M37221M4H/M6H/ M8H /MAH-XXXSP/FP and M37221EASP/FP have 2 pag.e register. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 91 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Internal State of Processor Status Register and Program Counter at Reset Name Function bit : : No function bit 0 : Fix to this bit to "0" (do not write to "1") 1 : Fix to this bit to "1" (do not write to "0") Register b7 Processor status register (PS) Program counter (PCH) Program counter (PCL) Bit allocation N V T B D I Z C State immediately after reset b0 b7 b0 ?????1?? Contents of address FFFF16 Contents of address FFFE16 Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 92 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Structure of Register The figure of each register structure describes its functions, contents at reset, and attributes as follows: CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 00 11 Bit position Bit attributes(Note 2) Values immediately after reset release (Note 1) CPU mode register (CPUM) (CM) [Address 00FB16] Name 0, 1 Processor mode bits (CM0, CM1) B Functions b1 b0 After reset R W 0 RW 0 0 1 1 0: Single-chip mode 1: 0: Not available 1: 1 1 1 0 RW RW RW RW 2 Stack page selection bit (See note) (CM2) 0: 0 page 1: 1 page 3, 4 Fix these bits to "1." 5 Nothing is assigned. This bit is write disable bit. When this bit is read out, the value is "1." b7 b6 Clock switch bits 6, 7 (CM6, CM7) 0 0: f(XIN) = 8 MHz 0 1: f(XIN) = 12 MHz 1 0: f(XIN) = 16 MHz 1 1: Do not set : Bit in which nothing is assigned Notes 1: Values immediately after reset release 0 ******************"0" after reset release 1 ******************"1" after reset release Indeterminate***Indeterminate after reset release 2: Bit attributes******The attributes of control register bits are classified into 3 types : read-only, write-only and read and write. In the figure, these attributes are represented as follows : R******Read W******Write W ******Write enabled R ******Read enabled - ******Read disabled - ******Write disabled ******"0" can be set by software, but "1" cannot be set. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 93 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Addresses 00C116, 00C316, 00C516 Port Pi Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (Di) (i=0,1,2) [Addresses 00C1 16, 00C316, 00C516] B 0 1 2 3 4 5 6 7 Name Port Pi direction register Functions 0 : Port Pi0 input mode 1 : Port Pi0 output mode 0 : Port Pi1 input mode 1 : Port Pi1 output mode 0 : Port Pi2 input mode 1 : Port Pi2 output mode 0 : Port Pi3 input mode 1 : Port Pi3 output mode 0 : Port Pi4 input mode 1 : Port Pi4 output mode 0 : Port Pi5 input mode 1 : Port Pi5 output mode 0 : Port Pi6 input mode 1 : Port Pi6 output mode 0 : Port Pi7 input mode 1 : Port Pi7 output mode After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW Address 00C716 Port P3 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P3 direction register (D3) [Address 00C716] Functions 0 : Port P30 input mode 1 : Port P30 output mode 0 : Port P31 input mode 1 : Port P31 output mode 0 : Port P32 input mode 1 : Port P32 output mode After reset R W 0 0 0 RW RW RW B 0 1 2 Name Port P3 direction register 3 to 7 Nothing is assigned. These bits are write disable bits. When these b its are read out, the values are indeterminate . indeterminate R -- Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 94 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00CB16 Port P5 Direction Register b7 b6 b5 b4 b3 b2 b1 b0 Port P5 direction register (D5) [Address 00CB16] b Name Functions After reset R W 0 0 0 0 0 R-- RW RW RW RW 0, 1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 3 4 5 Port P52 output signal selection bit (P52SEL) Port P53 output signal selection bit (P53SEL) Port P54 output signal selection bit (P54SEL) Port P55 output signal selection bit (P55SEL) 0 : R signal output 1 : Port P52 output 0 : G signal output 1 : Port P53 output 0 : B signal output 1 : Port P54 output 0 : OUT1 signal output 1 : Port P55 output 6,7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0. Indeterminate R -- Address 00CD16 P3 output mode control register b7 b6 b5 b4 b3 b2 b1 b0 P3 output mode control register(P3S) [Address 00CD16] B 0 1 2 3 Name P30 output form selection bit (P30S) P31 output form selection bit (P31S) DA1 output enable bit (DA1S) DA2 output enable bit (DA2S) Functions 0: CMOS output 1: N-channel open-drain output 0: CMOS output 1: N-channel open-drain output 0: P30 input/output 1: DA1 output 0: P31 input/output 1: DA2 output After reset R W 0 0 0 0 0 RW RW RW RW R-- 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 95 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00D516 PWM Output Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 1 (PW) [Address 00D516] B Name Functions 0 DA, PWM count source 0 : Count source supply 1 : Count source stop selection bit (PW0) 0 : DA output 1 DA/PN4 selection bit 1 : PN4 output (PW1) 2 P00/PWM0 output selection bit (PW2) 3 P01/PWM1 output selection bit (PW3) 4 P02/PWM2 output selection bit (PW4) 5 P03/PWM3 output selection bit (PW5) 6 P04/PWM4 output selection bit (PW6) 7 P05/PWM5 output selection bit (PW7) 0: P00 output 1: PWM0 output 0: P01 output 1: PWM1 output 0: P02 output 1: PWM2 output 0: P03 output 1: PWM3 output 0: P04 output 1: PWM4 output 0: P05 output 1: PWM5 output After reset R W 0 RW 0 0 0 0 0 0 0 RW RW RW RW RW RW RW Address 00D616 PWM Output Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 PWM output control register 2 (PN) [Address 00D616] B Name Functions After reset R W 0,1 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 2 DA output polarity selection bit (PN2) 3 PWM output polarity selection bit (PN3) 4 DA general-purpose output bit (PN4) 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Output LOW 1 : Output HIGH 0 0 0 0 R-- RW RW RW 5 Nothing is assigned. These bits are write disable bits. to When these bits are read out, the values are "0." 7 0 R-- Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 96 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00D716 I2C Data Shift Register b7 b6 b5 b4 b3 b2 b1 b0 I2C data shift register (S0) [Address 00D716] B 0 to 7 Name Functions After reset Indeterminate RW RW D0 to D7 This is an 8-bit shift register to store receive data and write transmit data. Note: To write data into the I2C data shift register after setting the MST bit to "0" (slave mode), keep an interval of 8 machine cycles or more. Address 00D816 I2C Address Register b7 b6 b5 b4 b3 b2 b1 b0 I2C address register (S0D) [Address 00D816] B 0 Name Read/write bit (RBW) Functions After reset R W 0 R-- 1 to 7 Slave address (SAD0 to SAD6) 0 RW Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 97 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00D916 I2C Status Register b7 b6 b5 b4 b3 b2 b1 b0 I2C status register (S1) [Address 00D916] B 0 1 2 3 4 5 Name Last receive bit (LRB) (See note) General call detecting flag (AD0) (See note) Slave address comparison flag (AAS) (See note) Arbitration lost detecting flag (AL) (See note) I2C-BUS interface interrupt request bit (PIN) Bus busy flag (BB) Functions 0 : Last bit = "0 " 1 : Last bit = "1 " (See note) After reset R W Indeterminate 0 0 R-- R-- R-- R-- RW RW RW 0 : No general call detected 1 : General call detected (See note) 0 : Address mismatch 1 : Address match 0 : Not detected 1 : Detected (See note) 0 1 0 0 (See note) 0 : Interrupt request issued 1 : No interrupt request issued 0 : Bus free 1 : Bus busy b7 0 0 1 1 b6 0 : Slave recieve mode 1 : Slave transmit mode 0 : Master recieve mode 1 : Master transmit mode 6, 7 Communication mode specification bits (TRX, MST) Note : These bits and flags can be read out, but cannnot be written. Address 00DA16 I2C Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C control register (S1D) [Address 00DA16] B 0 to 2 Name Bit counter (Number of transmit/recieve bits) (BC0 to BC2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0: 8 1: 7 0: 6 1: 5 0: 4 1: 3 0: 2 1: 1 After reset R W 0 RW 3 4 5 I2C-BUS interface use enable bit (ESO) Data format selection bit(ALS) Addressing format selection bit (10BIT SAD) 0: Disabled 1: Enabled 0: Addressing format 1: Free data format 0: 7-bit addressing format 1: 10-bit addressing format b7 b6 Connection port (See note) 0 0: None 0 1: SCL1, SDA1 1 0: SCL2, SDA2 1 1: SCL1, SDA1, SCL2, SDA2 0 0 0 0 RW RW RW RW 6, 7 Connection control bits between I2C-BUS interface and ports (BSEL0, BSEL1) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 98 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00DB16 I2C Clock Control Register b7 b6 b5 b4 b3 b2 b1 b0 I2C clock control register (S2) [Address 00DB16] B 0 to 4 Name Functions After reset R W 0 SCL frequency control bits Setup value of Standard clock High speed (CCR0 to CCR4) CCR4-CCR0 mode clock mode 0 0 to 0 2 03 04 05 06 1D 1E 1F ... Setup disabled Setup disabled Setup disabled Setup disabled 100 83.3 17.2 16.6 16.1 333 250 400 (See note) 166 34.5 33.3 32.3 RW 500/CCR value 1000/CCR value (at = 4 MHz, unit : kHz) 5 SCL mode specification bit (FAST MODE) ACK bit (ACK BIT) ACK clock bit (ACK) 0: Standard clock mode 1: High-speed clock mode 0: ACK is returned. 1: ACK is not returned. 0: No ACK clock 1: ACK clock 0 RW RW RW 6 7 0 0 Note: At 400 kHz in the high-speed clock mode, the duty is as below . "0" period : "1" period = 3 : 2 In the other cases, the duty is as below. "0" period : "1" period = 1 : 1 Address 00DC16 Serial I/O Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Serial I/O mode register (SM) [Address 00DC16] B Name b1 b0 Functions 0 0: f(XIN)/4 0 1: f(XIN)/16 1 0: f(XIN)/32 1 1: f(XIN)/64 0: External clock 1: Internal clock 0: P20, P21 1: SCLK, SOUT 0, 1 Internal synchronous clock selection bits (SM0, SM1) After reset R W 0 RW 2 3 Synchronous clock selection bit (SM2) Serial I/O port selection bit (SM3) 0 0 RW RW 4 Fix this bit to "0." 5 6 7 Transfer direction selection bit (SM5) Serial input pin selection bit (SM6) 0: LSB first 1: MSB first 0: Input signal from SIN pin. 1: Input signal from SOUT pin. 0 0 0 0 RW RW RW R-- Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 99 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Addresses 00DE16 and 00DF16 DA conversion register i b7 b6 b5 b4 b3 b2 b1 b0 0 DA conversion register i (i=1, 2) (DAi) [Addresses 00DE16, 00DF16] B Name b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 0/64Vcc 1 : 1/64Vcc 0 : 2/64Vcc After reset R W 0 RW 0 DA conversion to selection bit 5 (DAi0 to DAi5) 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 61/64Vcc 0 : 62/64Vcc 1 : 63/64Vcc 6 7 Fix this bit to "0." Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 0 RW R-- Note : When use M37221M4H/M6H/M8H/MAH-XXXSP/FP, there is not this register. Fix to " 0016." Address 00E016 Horizontal Position Register b7 b6 b5 b4 b3 b2 b1 b0 Horizontal position register (HR) [Address 00E0 16] B 0 to 5 Name Horizontal display start positions (HR0 to HR5) Functions 64 steps (0016 to 3F16) After reset R W 0 0 RW R-- 6, 7 Nothing is assigned. These bits are write disable bits. When thses bits are read out, the values are "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 100 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Addresses 00E116 and 00E216 Vertical Position Register i b7 b6 b5 b4 b3 b2 b1 b0 Vertical position register i (CVi) (i = 1 and 2) [Addresses 00E1 16, 00E216] B 0 to 6 7 Name Functions After reset RW Vertical display start positions 128 steps (0016 to 7F16) (CVi : CVi0 to CVi6) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Indeterminate R W 0 R-- Address 00E416 Character Size Register b7 b6 b5 b4 b3 b2 b1 b0 Character size register (CS) [Address 00E416] B Name Functions 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. 00 : Minimum size 01 : Medium size 10 : Large size 11 : Do not set. After reset Indeterminate RW RW 0, 1 Character size of block 1 selection bits (CS10, CS11) 2,3 Character size of block 2selection bits (CS20,CS21) 4 to 7 Indeterminate RW Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 101 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00E516 Border Selection Register b7 b6 b5 b4 b3 b2 b1 b0 Border selection register (MD) [Address 00E5 16] B 0 1 2 3 to 7 Name Functions After reset R W Block 1 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD10) 1 : Border output Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 0 R-- Block 2 OUT1 output 0 : Same output as R, G, B is output Indeterminate R W border selection bit (MD20) 1 : Border output Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Addresses 00E616 to 00E916 Color Register i b7 b6 b5 b4 b3 b2 b1 b0 Color regist er i (COi) (i = 0 to 3) [Addresses 00E616 to 00E916] B 0 1 2 3 4 5 6 7 Name Functions After reset R W 0 0 0 0 0 0 0 0 R-- RW RW RW RW RW RW RW Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." B signal output selection bit (COi1) G signal output selection bit (COi2) R signal output selection bit (COi3) 0: No character is output 1: Character is output 0: No character is output 1: Character is output 0: No character is output 1: Character is output B signal output (background) 0: No background color is output selection bit (COi4) (See note 1) 1: Background color is output OUT1 signal output control bit (COi5) (See notes 1, 2) 0: Character is output 1: Blank is output 0: No background color is output G signal output (background) selection bit (COi6) (See note 1) 1: Background color is output R signal output (background) 0: No background color is output selection bit (COi7) (See note 2) 1: Background color is output Notes 1: When bit 5 ="0" and bit 4 = "1," there is output same as a character or border output from pin OUT1. Do not set bit 5 = "0" and bit 4 = "0." 2: When only bit 7 ="1" and bit 5 "0," there is output from pin OUT2. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 102 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00EA16 OSD Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD control register (CC) [Address 00EA16] B 0 1 2 3 to 6 7 Name All-blocks display control bit (CC0) (See note) Block 1 display control bit (CC1) Block 2 display control bit (CC2) Functions 0 : All-blocks display off 1 : All-blocks display on 0 : Block 1 display off 1 : Block 1 display on 0 : Block 2 display off 1 : Block 2 display on After reset R W 0 0 0 0 RW RW RW R-- Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." P10/OUT2 pin switch bit (CC7) 0 : P10 1 : OUT2 0 RW Note: Display is controlled by logical product (AND) between the all-blocks display control bit and each block control bit. Addresses 00EC16 OSD Port Control Register b7 b6 b5 b4 b3 b2 b1 b0 OSD port control register (CRTP) [Address 00EC16] B 0 1 2 3 4 5 6 7 Name HSYNC input polarity switch bit (HSYC) VSYNC input polarity switch bit (VSYC) Functions 0 : Positive polarity input 1 : Negative polarity input 0 : Positive polarity input 1 : Negative polarity input After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW R/G/B output polarity switch 0 : Positive polarity output 1 : Negative polarity output bit (R/G/B) OUT2 output polarity switch bit (OUT2) OUT1 output polarity switch bit (OUT1) R signal output switch bit (OP5) G signal output switch bit(OP6) B signal output switch bit(OP7) 0 : Positive polarity output 1 : Negative polarity output 0 : Positive polarity output 1 : Negative polarity output 0 : R signal output 1 : MUT E signal output 0 : G signal output 1 : MUT E signal output 0 : B signal output 1 : MUT E signal output Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 103 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00ED16 OSD Clock Selection Register b7 b6 b5 b4 b3 b2 b1 b0 000000 OSD clock selection register (CK) [Address 00ED16] B Name Functions After reset R W 0 RW 0, 1 OSD clock Functions b1 b0 selection bits 0 0 The clock for display is supplied by connecting RC (CK0,CK1) or LC across the pins OSC1 and OSC2. 0 1 Since the main clock is used as the clock for display, the oscillation frequency is limited. Because of this, the character size in width (horizontal) 0 direction is also limited. In this case, pins OSC1 and OSC2 are also used as input ports P33 and P34 respectively. 1 OSD oscillation frequency = f(XIN) OSD oscillation frequency = f(XIN)/1.5 1 1 The clock for OSD is supplied by connecting the following across the pins OSC1 and OSC2. * a ceramic resonator only for OSD * a quartz-crystal oscillator only for OSD and a feedback resistor (See note) 0 RW 2 to 7 Fix these bits to "0." Note: It is necessary to connect other ceramic resonator or quartz-crystal oscillator for OSD across the pINs XIN and XOUT. Addresses 00EE16 A-D Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 1 (AD1) [Address 00EE16] B 0 to 2 Name Analog input pin selection bits (ADM0 to ADM2) b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 Functions b0 0 : A-D1 1 : A-D2 0 : A-D3 1 : A-D4 0 : A-D5 1 : A-D6 0 : Do not set 1 : Do not set After reset R W 0 RW 3 4 5 to 7 This bit is a write disable bit. When this bit is read out, the value is "0." Storage bit of comparison result (ADM4) 0: Input voltage < reference voltage 1: Input voltage > reference voltage 0 Indeterminate 0 R-- R-- R-- Nothing is assigned. This bits are write disable bits. When these bits are read out, the values are "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 104 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00EF16 A-D Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 A-D control register 2 (AD2) [Address 00EF16] B 0 to 5 Name D-A converter set bits (ADC0 to ADC5) b5 0 0 0 b4 0 0 0 b3 0 0 0 Functions b2 0 0 0 b1 0 0 1 b0 0 : 1/128Vcc 1 : 3/128Vcc 0 : 5/128Vcc After re set R W 0 RW 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 : 123/128Vcc 0 : 125/128Vcc 1 : 127/128Vcc 0 R-- 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are reed out, the values are " 0." Addresses 00F416 Timer 12 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 0 Timer mode register (T12M) [Address 00F416] B 0 1 Name Functions After reset R W 0 0 0 0 0 RW RW RW RW RW Timer 1 count source 0: f(XIN)/16 selection bit 1 (T12M0) 1: f(XIN)/4096 Timer 2 count source selection bit (T12M1) 0: Interrupt clock source 1: External clock from TIM2 pin 0: Count start 1: Count stop 0: Count start 1: Count stop 0: f(XIN)/16 1: Timer 1 overflow 2 Timer 1 count stop bit (T12M2) 3 Timer 2 count stop bit (T12M3) 4 Timer 2 internal count source selection bit 2 (T12M4) 5 Fix this bit to "0." 0 0 RW R-- 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 105 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00F516 Timer 34 Mode Register b7 b6 b5 b4 b3 b2 b1 b0 Timer 34 mode register (T34M) [Address 00F516] B Name 0 Timer 3 count source selection bit (T34M0) 1 Timer 4 internal interrupt count source selection bit (T34M1) Functions 0 : f(XIN)/16 1 : External clock source 0 : Timer 3 overflow signal 1 : f(XIN)/16 0: Count start 1: Count stop 0: Count start 1: Count stop 0: Internal clock source 1: f(XIN)/2 After reset R W 0 RW 0 RW 2 Timer 3 count stop bit (T34M2) 3 Timer 4 count stop bit (T34M3) 4 Timer 4 count source selection bit (T34M4) 5 0 0 0 0 RW RW RW RW Timer 3 external count 0: TIM3 pin input source selection bit 1: HSYNC pin input (T34M5) 6, 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 0 R-- Addresses 00F916 Interrupt Input Polarity Register b7 b6 b5 b4 b3 b2 b1 b0 0 00 Interrupt input polarity register(RE) [Address 00F916 ] B Name Functions After reset R W 0 0 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 : Positive polarity 1 : Negative polarity 0 0 0 0 0 R-- RW RW RW RW R-- RW 0 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 1,2 Fix These bits to "0." 3 4 5 6 7 INT1 polarity switch bit (RE3) INT2 polarity switch bit (RE4) INT3 polarity switch bit (RE5) Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." Fix this bit to "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 106 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00FB16 CPU Mode Register b7 b6 b5 b4 b3 b2 b1 b0 11111 00 CPU mode register (CM) [Address 00FB16] B Name Functions After reset R W Indeterminate 0, 1 Fix these bits to "0." 2 Stack page selection bit (CM2) (See note) 0: 0 page 1: 1 page RW RW RW 1 Indeterminate 3 to 7 Fix these bits to "1." Note: This bit is set to "1" after the reset release. Addresses 00FC16 Interrupt Request Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16] B Name 0 Timer 1 interrupt request bit (TM1R) 1 2 3 4 5 6 7 Functions After reset 0 0 : No interrupt request issued 1 : Interrupt request issued 0 Timer 2 interrupt 0 : No interrupt request issued request bit (TM2R) 1 : Interrupt request issued 0 Timer 3 interrupt 0 : No interrupt request issued request bit (TM3R) 1 : Interrupt request issued 0 Timer 4 interrupt 0 : No interrupt request issued request bit (TM4R) 1 : Interrupt request issued OSD interrupt request 0 : No interrupt request issued 0 1 : Interrupt request issued bit (CRTR) VSYNC interrupt 0 0 : No interrupt request issued request bit (VSCR) 1 : Interrupt request issued 0 Multi-master I2C-BUS interface 0 : No interrupt request issued interrupt request bit (IICR) 1 : Interrupt request issued 0 0 : No interrupt request issued INT3 external interrupt request bit (IT3R) 1 : Interrupt request issued RW R R R R R R R R : "0" can be set by software, but "1" cannot be set. Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 107 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00FD16 Interrupt Request Register 2 b7 b6 b5 b4 b3 b2 b1 b0 0 Interrupt request register 2 (IREQ2) [Address 00FD16] B Name 0 INT1 external interrupt request bit (IT1R) 1 2 INT2 external interrupt request bit (IT2R) Functions After reset R W 0 : No interrupt request issued 0 R 1 : Interrupt request issued 0 : No interrupt request issued 0 R 1 : Interrupt request issued 0 0 0 0 0 R R-- R R-- RW 0 : No interrupt request issued 1 : Interrupt request issued 3 Nothing is assigned. This bit is a write disable bit. When this bit is read out, the value is "0." 4 f(XIN)/4096 interrupt 0 : No interrupt request issued request bit (MSR) 1 : Interrupt request issued 5, 6 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." 7 Fix this bit to "0." : "0" can be set by software, but "1" cannot be set. Serial I/O interrupt request bit (S1R) Addresses 00FE16 Interrupt Control Register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset R W 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW 0 Timer 1 interrupt enable bit (TM1E) 1 Timer 2 interrupt enable bit (TM2E) 2 Timer 3 interrupt enable bit (TM3E) 3 Timer 4 interrupt enable bit (TM4E) 4 OSD interrupt enable bit (CRTE) 5 VSYNC interrupt enable bit (VSCE) 6 Multi-master I2C-BUS interface 0 : Interrupt disabled interrupt enable bit (IICE) 1 : Interrupt enabled 7 INT3 external interrupt 0 : Interrupt disabled 1 : Interrupt enabled enable bit (IT3E) Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 108 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Address 00FF16 Interrupt Control Register 2 b7 b6 b5 b4 b3 b2 b1 b0 000 0 Interrupt control register 2 (ICON2) [Address 00FF16] B Name Functions 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled After reset 0 0 0 0 0 : Interrupt disabled 1 : Interrupt enabled 0 0 RW RW RW RW RW RW RW 0 INT1 external interrupt enable bit (IT1E) 1 INT2 external interrupt enable bit (IT2E) 2 Serial I/O interrupt enable bit (S1E) 3 Fix this bit to "0." 4 f(XIN)/4096 interrupt enable bit (MSE) 5 to 7 Fix these bits to "0." Addresses 021B16 ROM Correction Enable Register b7 b6 b5 b4 b3 b2 b1 b0 00 ROM correction enable register (RCR) [Address 021B16] B 0 1 Name Vector 1 enable bit (RCR0) Vector 2 enable bit (RCR1) Functions 0: Disabled 1: Enabled 0: Disabled 1: Enabled After reset R W 0 0 0 0 RW RW RW R-- 2, 3 Fix these bits to "0." 4 to 7 Nothing is assigned. These bits are write disable bits. When these bits are read out, the values are "0." Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 109 of 110 M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP 20. PACKAGE OUTLINE 42P4B EIAJ Package Code SDIP42-P-600-1.78 MMP JEDEC Code - Weight(g) 4.1 Lead Material Alloy 42/Cu Alloy Plastic 42pin 600mil SDIP 42 22 1 21 Symbol D e SEATING PLANE b1 b b2 A A1 A2 b b1 b2 c D E e e1 L Dimension in Millimeters Min Nom Max - - 5.5 0.51 - - - 3.8 - 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 - 1.778 - - 15.24 - 3.0 - - 0 - 15 A 42P2R-A/E EIAJ Package Code SSOP42-P-450-0.80 42 A1 L A2 Plastic 42pin 450mil SSOP JEDEC Code - Weight(g) 0.63 22 Lead Material Alloy 42 e e1 E c b2 HE E e1 F Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.4 0.3 0.25 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - - 0.75 - - - 0.9 0.15 - - 0 - 10 - 0.5 - - 11.43 - - 1.27 - Symbol 1 21 A G D A2 e y b A1 A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2 L1 c z Z1 Detail G Detail F Rev.1.00 Oct 01, 2002 REJ03B0134-0100Z page 110 of 110 L I2 REVISION HISTORY Rev. Date Page 1.00 Oct 01, 2002 - First edition issued M37221M4H/M6H/M8H/MAH-XXXSP/FP M37221EASP/FP Description Summary A-1 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. Unit2607 Ruijing Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 http://www.renesas.com (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .2.0 |
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